(Invited) Bulk Traps in Layered 2D Gate Dielectrics

The wearout of 4 nm to 13 nm thick oxides fabricated on n-type and p-type substrates was measured. The interface trap densities, flatband voltage shifts, bulk trap densities and low-level leakage currents were measured before and after high-voltage stressing. In oxides that had been stressed at the equivalent electric fields for constant times, the measured flatband voltage shifts, interface trap densities, and bulk trap densities dropped as the oxide thicknesses dropped and were negligible for oxides thinner than 6 nm, while the low-level pre-tunneling leakage currents increased. Both an AC and a DC component to the stress-induced low-level leakages were measured. The DC component to this leakage current increased as the oxide thicknesses decreased. A model based on uniform trap generation throughout the oxide during the high-voltage stresses and tunnel charge/discharge of the traps within approximately 3 nm of either interface after the stresses were removed, has been used to explain and accurately fit all of the thickness dependences of the trap generation and leakage current measurements. The thickness dependent leakage currents will limit oxides to thicknesses greater than about 10 nm for non-volatile memory applications.

Effect of fluorinated silicate glass passivation layer on electrical characteristics and dielectric reliabilities for the HfO 2/SiON gate stacked nMOSFET

This study analyzes the changes in the density of interface traps (DIT) for various atomic layer deposition (ALD) gate dielectric films on gallium nitride (GaN) devices fabricated on bulk GaN substrates. Each film type has been chosen with an optimized insulator/semiconductor interface obtained through chemical cleans or post deposition annealing (PDA). Reduction in dielectric leakage and interface traps in MOSCAP devices may be used in order to understand how these mechanisms affect more complex devices such as vertical GAN MOSFETs. GaN MOSFET and MOSCAP devices are often investigated and implemented in power systems with applications ranging from electric vehicles (EVs) to smart power grids. The unique material properties of GaN such as wide bandgap, high breakdown voltage, and high electron mobility create unique advantages over traditional silicon FETs. Vertical GAN MOSFETs are better suited for higher voltage applications due to current flow and voltage drop perpendicular to the surface while also reducing required chip area for high operating voltages. Although there are many advantages of vertical GaN devices, such an architecture presents unique challenges that must be addressed before such devices may be implemented in high power applications, such as the requirement for a native substrate and the need to improve the gate dielectric interface. The interface between the gate dielectric and the semiconductor is crucial in order to reduce threshold voltage drift, leakage current, and the density charge traps. Previous work has shown the importance of DIT reduction with chemical cleans and PDAs. Accurate calculations of the density of interface traps (DIT) are vital to fully realize device operation and reliability. The choice between surface cleans and dielectric annealing as a leakage reduction technique is dependent on the material and available processing capabilities. While PDAs may reduce the dielectric breakdown strength, they have been found to reduce gate leakage current and improve device performance for most gate dielectrics. Several methods have been proposed for DIT characterization, including the voltage dependencies of low- and highfrequency capacitance (CV), conductance (GV), and surface potential (WY). DIT may be calculated from the surface potential of the dielectric using the quasi-static capacitance and the capacitance of the chosen gate dielectric. This work uses quasi-static CV and surface potential electrical characterization of GAN MOSCAPs to determine DIT of various gate dielectric materials treated with PDAs and chemical cleans. Optimization of such films on MOSCAPs will allow for implementation into vertical GAN MOSFET architectures. Interface trap density may be reduced by decreasing the capacitance associated with defects and surface contamination or by selection of a dielectric material with a lower dielectric constant. Fixed charges at the dielectric/semiconductor interface are manifested in hysteresis between forward and reverse voltage sweeps and may be the result of contamination prior to ALD or point defects in the material. Al,0. is an attractive gate dielectric material due to its dielectric constant, which may improve breakdown strength (Fig. 1), but it may suffer from higher memory charge between continuous bias sweeps. SiO, ALD films have lower breakdown and significantly lower leakage currents but show the lowest density of remaining fixed charges between sweeps, suggestive of the lowest DIT of the tested dielectrics (Fig. 2) with the addition of PDA. Results were verified by altering bias conditions during testing in order to accumulate and deplete interface charges. Minor plateaus in capacitance in forward bias indicate the presence of negative fixed interface charges. Additional characterization may be necessary to determine the optimal conditions for DIT reduction for HfO., films, including reduction in PDA temperatures in combination with improved substrate chemical cleans.

Interface trap and bulk trap densities of atomic-layer-deposited (ALD) Si-nitride dielectrics have been evaluated by bipolar-voltage-pulse-induced current and electrical-stress-induced leakage-current measurements, respectively. In comparison with the conventional SiO2 dielectrics, significantly lower (∼1/3) interface trap density near the conduction band edge is observed in the ALD Si-nitride dielectrics. Moreover, the observed lower interface and bulk trap generations consistently explain the soft-breakdown-free phenomena observed in capacitors with the ALD Si-nitride gate dielectrics. Enhanced dielectric reliability and several other significant features have made the ALD Si-nitride gate dielectrics a front line candidate for extremely thin (equivalent oxide thickness ∼1 nm) gate dielectrics of sub-100-nm technology nodes.

Solution-processed lanthanum-doped Al2O3 gate dielectrics for high-mobility metal-oxide thin-film transistors

Reaction–diffusion in high- k dielectrics on Si

Properties of atomic-vapor and atomic-layer deposited Sr, Ti, and Nb doped Ta2O5 Metal–Insulator–Metal capacitors

Scaling silicon-based transistors to sub-ten-nanometer technology nodes presents significant challenges due to the difficult in achieving both atomic-scale thickness and excellent tunneling performance simultaneously. In this work, we employed first-principles calculations to investigate the dielectric properties of two recently reported van der Waals layered materials, Bi2SeO5 and Bi2TeO5. Our results reveal that Bi2SeO5 and Bi2TeO5 monolayers exhibit out-of-plane dielectric constant of 15.2 and 7.6, respectively, with in-plane dielectric constant reaching as high as 39.0 and 26.0. To evaluate their potential as gate dielectrics, we calculated the band offsets and equivalent oxide thicknesses (EOTs) of Bi2SeO5 and Bi2TeO5 monolayers. The results show that both materials exhibit favorable band offsets relative to silicon and transition-metal dichalcogenide channel materials, along with low EOT. Finally, we estimated the dielectric leakage current density utilizing Bi2SeO5 and Bi2TeO5 based on a p-doped silicon-channel transistor, predicting a low leakage current (<10−8 A cm−2). Our study provides theoretical insights into the potential application of bismuth selenite and bismuth tellurite monolayers as gate dielectrics in two-dimensional electronics.

This research focuses on the benefits and properties of TiO2–Al2O3 nanostack thin films deposited on Ga2O3/GaN by plasma-assisted atomic layer deposition (PA–ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films' structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO2, 7.1 nm Al2O3, and 2 nm Ga2O3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectron spectroscopy depth profile, was negligible for GaN pretreated by thermal oxidation in O2 for 30 min at 850 °C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nanostack, as determined by atomic force microscopy. The dielectric constant of TiO2–Al2O3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al2O3 (8–9) on GaN. In addition, the nanostack's capacitance–voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 1011 cm−2. The gate leakage current density (J = 2.81 × 10−8 A/cm2) was low at +1 V gate bias. These results demonstrate the promising potential of PA–ALD deposited TiO2/Al2O3 for serving as the gate dielectric on Ga2O3/GaN based MOS devices.

DRAM is a type of memory that stores each bit of data in a capacitor cell, leakage current is a very important electrical parameter to retain data. Therefore, larger cell capacitance and smaller leakage current have been regarded as key factors in continuous shrinkage of DRAM. Generally, gate induced drain leakage (GIDL) and junction leakage of cell transistor (CTR) are well-known, but our approach is focused on retention failure by bulk trap. In order to electrically observe the influence of bulk trap, we used the adjacent gate of CTR to control electron migration. Results show that there are many failure cells due to bulk trap, and dimension shrinkage accelerates this failure. Consequently, balancing among electrical bias point and transistor manufacturing process should be carefully considered with bulk traps.

Amorphous silicon nitride (a-SiNx) is widely used as the gate dielectric and passivation layer in a-Si:H based electronics. For devices on plastic substrates deposited at low temperature, the a-SiNx quality seems to determine the device performance. This paper investigates the effects of hydrogen dilution, helium dilution, ammonia-silane gas flow ratio, and RF power on the properties of PECVD silicon nitrides deposited in large-area parallel-plate reactors at substrate temperatures of 75°C. The chemical composition and bonding of the SiNx:H films was studied using FTIR spectroscopy. The physical properties were investigated, and the density, growth rate, and compressive stress of the films were determined. The electrical properties such as leakage current, breakdown, stability, trap density, and dielectric constant of the films were characterized by I-V and C-V measurements of metal-insulator semiconductor (MIS) structures. Analysis of Variance (ANOVA) was performed on the results, and the deposition conditions for the optimal film properties were determined. The optimum film had SiNx:H stoichiometry of x=1.56 with hydrogen concentrations of 17 at.%, and exhibited compressive stress of -220 MPa. The film displayed good stability under electrical stress with ohmic leakage of Rleak ∼1016 Ωcm. Strong relationships between the film properties and deposition conditions were observed, and are discussed within the paper. A-Si:H bottom gate TFTs were fabricated using the optimized nitrides for gate dielectrics and passivation layers, and the influence of a-SiNx on TFT performance is discussed.

An ultra-thin natural-source-based cellulose derivate is used in a bilayer gate dielectric for organic complementary inverters. Extraordinarily high small-signal gains up to 1600, a very sharp transition region (as low as 40 mV), a full rail-to-rail swing, a balanced noise margin of 92.5%, and “long-time” stability are shown, revealing that these inverters are highly suitable for complex circuit designs. For more than a decade now the research in organic electronics was driven by unique consumer markets demanding for electronic circuits on flexible substrates over large areas and ideally at low cost. Meanwhile, versatile macroelectronic applications with attractive form factors such as flexible displays,1-4 large-area sensor arrays,5-11 e-paper,12, 13 low-cost radio-frequency identification tags,14-18 and bendable microprocessors19 have been realized using organic thin-film transistors (OTFTs) as the essential element. In the majority of these applications OTFTs are integrated either in the form of arrays or as digital logic. The fundamental building block of digital logic is the inverter, a circuit that inverts an input signal. Much work has been devoted in the last five years to design unipolar inverters using p-type-only OTFTs.18-23 Unfortunately, unipolar logic based on single gate OTFTs always suffers from high power consumption and low noise margin coupled with high noise margin variability and therefore impedes the fabrication of complex circuits having hundreds or more logic gates.19, 22, 23 In this context, it stands beyond doubt that the integration of both n-type and p-type transistors in complementary organic-based circuits12 is very advantageous due to a lower power dissipation, higher noise margin, better operational stability, and easier design of the circuit.24-27 To date, several major obstacles complicated the development of organic complementary circuits, which are as follows: i) the lack of n-channel OTFTs with a performance comparable to the p-channel OTFTs, ii) the challenge of device stability (difficulty in fabricating OTFTs with hysteresis-free characteristics), and iii) the difficulty in fabricating sufficiently thin gate dielectrics allowing for low supply voltages. Although many recently reported complementary organic inverters are impressive with respect to their low operation voltages (≤5 V),27-36 high static gains (>100 V/V),25, 28, 30, 32 and large noise margins (>80%),25, 35, 37, 38 only few of those can combine low-voltage operation with high gain and sufficient immunity against electrical noise.39 Moreover, there have been few investigations of the influence of hysteresis and threshold voltage shifts on the inverter characteristics, which typically gives rise to electrical instabilities and performance limitations of those devices.32, 39 The inverter's noise margin is the most critical parameter, since it directly determines the maximum complexity of circuits.22 Particularly, interesting applications of organic electronic circuits are found in analog electronics that allow for the read-out and processing of signals from printed large-area sensors and form an interface to silicon electronics. Examples are analog-to-digital (A/D) converters, operational amplifiers, and comparators, all including several tens of transistors, thus requiring both high gain and a large noise margin to be functional as well as sufficient processability. It is interesting to note that the majority of organic complementary inverters already mentioned24-34, 36-40 relied on pentacene as the p-type semiconductor (14 incidences), fluorinated copper phthalocyanine (6 incidences), or N,N′-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (5 incidences) as the n-type material. On the contrary, the variation in gate dielectric materials that are used is much higher with an emphasis on hybrid dielectric systems. Hybrid systems allow accounting for both a high dielectric breakdown voltage and an engineered interface to the semiconductor. Moreover, the implementation of biodegradable and biocompatible materials represents a new niche in the organic electronics research, aimed to address the issues of cost and toxicity to humans and environment posed by nowadays electronics, a topic that was recently reviewed elsewhere.41-43 Accordingly, we have demonstrated the usage of a novel hybrid and biodegradable high-k gate dielectric material system based on a cellulose derivative for low-voltage complementary organic circuits with exceptional high noise margins.35 Previous work done in our laboratories demonstrated the fabrication feasibility of complex circuits, where the electrode patterning was performed by a self-aligned photolithography technique.44, 45 This process can easily be transferred to an anodized aluminum (Al2O3) + trimethylsilyl cellulose (TMSC) based bilayer system; the respective results will be published soon. To follow on this preliminary work we have developed an extraordinarily well-performing complementary inverter technology based on a hybrid dielectric composed of a bilayer of alumina (Al2O3) and trimethylsilyl cellulose (TMSC) and pentacene or C60 for the p-channel and the n-channel organic semiconductor, respectively. It outperforms any inverter reported so far with respect to the combination of excellent key parameters, such as record DC gain of above 500 V/V, low operation voltage of only 4 V, and large noise margin up to 92.5%. In order to clarify the origin for this high performance, special attention is given to the investigation of the semiconductor–dielectric interface, the semiconductor morphology, the nature of traps, the influence of mobility levels on the inverter performance and its long-term stability. This article is not meant to report new materials and systems, but rather find explanations and present a thorough analysis of the extraordinary performance of the cellulose derivative (TMSC) dielectric and the TMSC to semiconductor interface in organic field-effect transistors and simple inverter circuits. All OTFTs presented in this work have a bottom gate, top contact device architecture, as illustrated in Figure 1a. The transistor fabrication process is described in detail in the Experimental Section. The semiconducting layer is pentacene for p-type and C60 (fullerene) for n-type conduction. For the gate dielectric, an inorganic (Al2O3)–organic (TMSC) bilayer is chosen with 28 and 30 nm layer thickness, respectively. The dielectric properties of both single-layer TMSC films and bilayer Al2O3 + TMSC films, were investigated by current–voltage (I(V)), capacitance–frequency (C(f)), and capacitance–voltage (C(V)) measurements in appropriate capacitor structures with 72 nm insulator layer thickness of pure TMSC and 28 + 30 nm of bilayer film of Al2O3 + TMSC, respectively. In Figure 1b, the I(V) curves of a representative capacitor formed by a single layer cellulose dielectric is shown, whereas in Figure S1a (in the Supporting Information) the curve with bilayer dielectric is displayed. A comparison of I(V) curves of a single layer and bilayer dielectric is displayed in Figure 1c. At an electric field of 3.0 MV cm−1 (equivalent to ≈22 V) a current density on the order of 10−6 A cm−2 is observed for the single-layer TMSC. A breakdown field of 4.5 ± 0.3 MV cm−1 is extracted from eight appropriate capacitor structures. One representative C(V) measurement is displayed in Figure 1d. Its capacitance of about 29 nF cm−2 corresponds to a dielectric constant of εR = 2.4 ± 0.2 at 1 kHz with an excellent stability at frequencies down to 0.5 mHz (virtually flat dielectric constant and low dielectric losses which are indicative of a high purity and negligible amount of mobile ionic species) as illustrated in Figure 1e.46 In comparison, capacitors based on the bilayer dielectric have three orders of magnitude lower leakage currents (≈10−9 A cm−2) at an electric field of 3.0 MV cm−1 corresponding to ≈17.5 V and an effective capacitance of 53 nF cm−2 at 1 kHz (see Figure S1a,b, Supporting Information). As can be derived from Figure S1c (in the Supporting Information) the permittivity of the bilayer dielectric also shows excellent stability over the tested frequency range (1 mHz to 10 kHz). The measured capacitance value of the dielectric is in good agreement with calculations by assuming a permittivity of 9 and a thickness of 28 nm for the Al2O3 layer as well as a measured permittivity of 2.4 ± 0.2 (Figure 1e) and 30 nm thickness for the TMSC layer (see the Experimental Section). In any OTFT with bottom gate architecture the surface properties of the gate dielectric (surface energy, surface roughness) decisively affect the arrangement and growth of small molecule semiconductors. The surface energy of spin-coated TMSC thin films was determined by contact angle measurements. With a water contact angle of 98.5°, TMSC can be regarded as a hydrophobic, low energy surface material with a total surface energy of γ = 24.2 ± 0.6 mN m−1, separable in a small polar component γP = 1.8 ± 0.5 mN m−1 and a dispersive component γD = 22.4 ± 0.1 mN m−1. The average surface roughness, indicated by the root mean square (rms)–roughness values, was found to be only 0.77 ± 0.1 nm by atomic force microscopy (AFM) measurements. On this smooth and low energy TMSC surface, a small-grain growth mode with average grain sizes between 150 and 300 nm for pentacene (shown in Figure 1a) and 50 nm for C60 was observed by AFM measurements. In Figure 2, typical electrical characteristics of OTFTs with either C60 or pentacene as the semiconducting layer are plotted. Both p- and n-type transistors are based on the inorganic–organic bilayer gate dielectric composed of Al2O3 and TMSC. The output characteristics ID(VDS) are displayed in Figure 2a,b, whereas the transfer characteristics ID(VGS) are shown in Figure 2c,d. Both transistor types display very small hysteresis between forward and reverse voltage sweeps. The output characteristics show clear saturation, but for the pentacene-based OTFT a non-linear behavior of the drain current at very low drain voltages is observable (Figure 2b). Such an S-shape of the output curve has been already observed and reported for many different device configurations and has sometimes been attributed to a lateral field dependent contact resistance.47-55 In Table 1, the critical device parameters Von (onset voltage), Vthr (threshold voltage), S (subthreshold swing), μlin (charge carrier mobility in the linear regime), and μsat (charge carrier mobility in the saturation regime) are compiled and averaged over eight devices for each transistor type. On average, C60-based OTFTs show a charge carrier mobility of 0.7 cm2 V−1 s−1 in the saturation regime, a threshold voltage of 1.3 V, and a small subthreshold swing of 305 mV dec−1. Pentacene-based OTFTs have on average a mean threshold voltage of −4.7 V, a very small subthreshold swing of 225 mV dec−1, and a field-effect mobility of 0.22 cm2 V−1 s−1 in the saturation regime. The gate leakage currents are very low and in the range of 10−10 A. The balanced performance of our p- and n-type OTFTs, as well as the fact that both transistor types strictly behave as normally off transistors at zero applied gate voltage is a good base for integrating them in complementary organic inverters. A schematic image of such a complementary inverter circuit is displayed in Figure 3a together with the voltage transfer characteristics (VTCs) of a typical device and the static gain measured for operation voltages of VDD = 4, 5, 6, and 7 V. The inverter exhibits extraordinarily high small-signal gains; for all operation voltages, gains above 500 V/V are measured with a maximum value of about 1000 V/V for VDD = 7 V. The best performing device even has a maximum gain value of 1600 V/V. Moreover, a very sharp transition regime (ΔVin ≤ 40 mV) and a full rail-to-rail swing are observed. The extracted inverter parameters are compiled in Table 2. The switching threshold voltages VM are found to be very close to the ideal value of VDD/2 at all operation voltages with a nearly perfect fit (e.g., VM = 2.04 V at VDD = 4 V). In Figure 3b, the mismatches of the threshold voltages to the ideal values (ΔVM) are plotted as a function of VDD revealing a linear increase of ΔVM with the supply voltage. This means that the asymmetry of the VTCs increase with increasing the operation voltages. Additionally, the noise margins (NM) are plotted in Figure 3b as a function of VDD, illustrating the linear decrease of the NM with increasing operation voltage. Such a behavior reveals the direct correlation between ΔVM and NM and is an indication of the deviation of the VTCs from perfect symmetry. The noise margin is an important figure of merit of an inverter stage and measures the immunity against inevitable transistor parameter variations and electrical noise.56 There are several ways to determine the noise margin of an inverter. One convenient way is called the “maximum equal criterion” (MEC), where the NM is found by the maximum square that fits between inverter transition curve and the mirrored inverter curve as shown in Figure 3c.22, 35 The NM values for all the supplied voltages are listed in Table 2. The noise margin is mainly limited by the steepness of the transition ΔVin and the position of the switching threshold voltage VM (VM = Vin = Vout) as shown in Figure 3c. High and balanced noise margins are found when the ideal condition VM = VDD/2 is met, thus when VM = Vin =VDD/2 = Vout. The inverter in Figure 3c has a NM of 1.79, which is 90% of the maximum theoretical value for a supply voltage of 4 V, determined by the “maximum equal criterion.” Additionally, the “negative slope criteria” reveals a balanced NM of 1.85 V (92.5%) for a supply voltage of 4 V. The OTFTs with pentacene and C60 semiconductor layers (as used in the complementary inverters) were also analyzed with regard to their long-term stability. The dependence of their onset voltage and charge carrier mobility on the time period after preparation is plotted in Figure 4 based on measurements of at least five devices for each transistor type. The error bars display the standard deviations. p- and n-type devices exhibit an onset voltage shift of +1.3 and +0.95 V, respectively, over a period of 45 days. The main part of the shift occurred either after the first or after the second measurement and then the onset voltage shift tended to saturate. It seems that both pentacene- and fullerene-based devices stabilized their electrical properties after few days. Between day 8 and day 45 no significant change in the transfer characteristics was observed. Concerning the subthreshold swing, no significant change was observed over 45 days (S = 215 mV dec−1 (0 days), 210 mV dec−1 (8 days), and 225 mV dec−1 (45 days)) in the pentacene OTFTs, indicating that the interface trap density is stable. On the contrary, after 8 days an increase of the swing was observed for the C60 devices from 305 mV dec−1 (0 days), to 410 mV dec−1 (8 days), to 430 mV dec−1 (45 days). The mean value of the charge carrier mobility of the pentacene OTFTs showed no significant variation over 45 days: 0.22 cm2 V−1 s−1(fresh sample), 0.19 cm2 V−1 s−1 (after 8 days), 0.21 cm2 V−1 s−1 (after 45 days). In contrast, a strong reduction of about one order of magnitude (from 0.7 to 0.06 cm2 V−1 s−1 within the first 8 days and to 0.05 cm2 V−1 s−1 after 45 days) was observed for the fullerene transistors. In order to test the reliability of our OTFT devices we have also performed negative and positive bias stress tests. The bias stress was done 1 day after fabrication, on devices which had been previously measured only once. A reversible negative onset voltage shift of about 400 mV was observed under negative bias of −7.5 V over 21 hours stress (see Figure 5a,b) The main part of the negative voltage shift occurred during the first 2 hours (300 mV) whereas shift saturation was reached after 6 hours. The positive bias stress resulted in a significantly smaller positive onset voltage shift (ca. +100 mV over 4 hours stressing the device). Devices that were stored for seven months in the glovebox showed no bias stress effect at all (i.e., shift of the onset voltage) when their transistor characteristics were measured at regular intervals during the storage period. In order to investigate the “long-time” behavior of complementary inverters, electrical measurements were done after 1, 4, 8, and 45 days of the respective device preparation. Inverters were measured 1 day after device stabilization (see Figure 4a,b). The “long-time” behavior of complementary inverters is shown in Figure 4c,d where the VTC and gain curves are plotted as a function of time. For the lowest VDD of only 4 V, a small shift of the switching threshold voltage was measured: starting from 2.04 V after 1 day to an identical value of 2.17 V after 8 and 45 days, respectively, with a related exceptional high noise margin of 1.79 V (90% of the theoretical maximum) after 1 day and 1.74 V (87%) after 8 and 45 days. It is interesting to note that, after 8 days of storage time, the hysteresis in inverter characteristics was virtually negligible (<100 mV, see Figure 4d) and moreover, repeated measurements did not change the inverter transition, although the gain was somewhat reduced (from 503 (0 days) to 320 (8 days) and 195 (45 days)). The operational stability of the VTC was shown over a period of at least 45 days (Figure 4c for VDD = 4 V). Furthermore, the remarkable long-term stability of these TMSC-based complementary inverters was demonstrated by 16 consecutively recorded inverter curves that are virtually superimposed over one another (Figure 5c). The current–voltage characteristics show that the Al2O3 + TMSC bilayer capacitors have substantially lower leakage currents than the single TMSC layer devices. Due to the roughness of the aluminum bottom electrode with spikes up to 10 nm, the anodization process is a convenient method to reduce the leakage currents for at least three orders of magnitude at an electric field of 3 MV cm−1 as displayed in Figure 1d and make the dielectric layer more robust.57 Another advantage of the anodization step is the substitution of the hydroxide of the native oxide layer. Finally, the subsequent short oxygen plasma treatment (see the Experimental Section) is sufficiently removing all residuals left after the anodization process. This procedure allows for the generation of a pure and trap-reduced dielectric interface to the organic semiconductors, by measurements at low revealing a virtually flat permittivity in the mHz to kHz frequency range and low dielectric losses which both are indicative of a high purity and negligible amount of mobile ionic The generation of this excellent interface is in virtually hysteresis-free characteristics of all the One important that the performance of OTFTs, and in the charge carrier is the of the As shown by several the of the surface energy of the to that of the is one important the growth For a low surface energy material with a smooth surface TMSC, a growth mode is and with a rather high density and small grain sizes are formed (see Figure The high density of grain a significant decrease of the charge carrier since grain as charge On the a better between pentacene on low surface energy materials TMSC with and better reduce the of trap thus the mobility of charge in the In there is an between grain related and interface with regard to their influence on charge carrier The low subthreshold swing observed in all our pentacene-based OTFTs is indicative of a low interface trap density which the influence of the large grain trap density on the charge carrier Accordingly, a mobility 0.2 cm2 V−1 s−1 is observed in the p-type devices. In C60 films, the influence of on the charge carrier mobility is by far not as significant as in pentacene films, which is attributed to the of the fullerene In the pentacene OTFTs (see Figure a non-linear current increase in the linear regime of the ID(VDS) output characteristics is at higher gate have been in to such a which can be observed in bottom gate The explanations i) the of the charge carrier mobility for semiconductor ii) currents that the of the mobile by an effective under the drain and iii) large at the electrode from an energy between the work of contact material and semiconductor films, a gate or large contact are found in our of these it has been shown that a mobility in combination with a small contact in a non-linear drain voltage dependence of the current due to The from a of from trap and a dependence of on the drain A respective of the pentacene output curve in Figure the dependence in the regime 2 V, thus indicating that a mobility has to be The of any hysteresis in the I(V) curves and the low and value of the subthreshold swing a low density of interface in the pentacene are not for the observed and the of the as by the of the pentacene layer gives rise to which to a field dependence of the charge carrier This is all the more given that the pentacene grain sizes are 300 nm at a large density of grain As by Figure 4 the characteristics of both pentacene- and C60-based OTFTs show a positive onset voltage shifts storage which after a of measurements. The virtually subthreshold swing in pentacene as well as the negligible hysteresis as the origin of the On the contrary, it seems that trap are for the positive onset voltage shift in are either over time or during the first measurements by the applied positive gate be easily by the gate bias and therefore are not to the swing, but the small onset voltage in pentacene-based It has been reported by many that the of the of trap in pentacene trap also be due to such as at the a at the or a at the fabrication and transfer from the to the measurement stage the semiconductor layer and rise to such For oxygen can even the devices are to but transferred directly and measured in a glovebox with reduced oxygen and water have also observed that the of oxygen with pentacene is in the that these are under device operation with the of oxygen in the grain observed that the storage of devices in and their subsequent measurement in did not a change in their I(V) also observed that the storage time to the first measurement has influence on the device (i.e., on the onset voltage in this of and the first measurement the of to the of oxygen or with the which in a second are by Moreover, also are are not as in the as the (see and This an for the positive shift of the onset voltage between first and second measurement (Figure and also for the saturation of the onset voltage shift in In order to clarify which of are present in our we performed measurements on pentacene films (in and after storage in for (see Figure Supporting Information). storage under a small increase of the at energy is observed that can be attributed to the to and The analysis reveals an increase of the from 0.2 to At the position no change is that trap in our devices for bias stress and the positive onset voltage can mainly be attributed to It be that the of any mobility in pentacene OTFTs against an of pentacene both are to oxygen For the C60 transistors, one a strong decrease of the charge carrier mobility during 8 days of storage which is by all over the device grain This is a effect of The decrease in charge carrier mobility and the at the interface that the subthreshold swing is in a positive onset voltage shift of the C60 transistors. With respect to the complementary inverters, noise margin values beyond from the maximum theoretical value for all supply voltages are and the high operational of the OTFT devices. At a very low supply voltage of 4 V, our bilayer organic complementary inverters have a static gain of more than 500 V/V with a noise margin of 92.5%, which is already reported devices with architecture (see the of inverter performance given in 38 and also gain values above 1000 V/V values up to 1600 were measured for our devices. This is all the most as the charge carrier mobility values of the transistors are not thus the that the of the mobility values between p- and n-channel with the virtually hysteresis are the factors for high gain and high noise margin Accordingly, a mobility 1 be the the is not high ≤ it can be by and p-channel transistors with different In our the mobility is The static of a complementary inverter is determined by technology parameters, the parameters of p- and n-type transistors. A good of these parameters a good saturation of both output can to a significant increase of the gain A is shown in the Supporting Furthermore, high gain values are also determined by the interface An insulator with an low trap density (as this is the for is in having I(V) curves with virtually zero Accordingly, it is to measurements with a very high voltage small voltage thus one to the high gain value of the complementary inverter it by hysteresis The noise margin with increasing VDD due to their strong this is also for the of the VTCs by see Figure A for this behavior can be found in the bias stress that was observed for both types of transistors. The negative shift of Von under negative gate and the positive

Capacitors play an increasingly important role in hybrid integrated circuits, while the MIM capacitors with high capacitance density and small thickness can meet the needs of high integration. Generally speaking, the films prepared with a single metal oxide dielectric often achieve a breakthrough in one aspect of performance, but dielectric layers are required to be improved to get better performance in leakage current, capacitance density, and transmittance simultaneously in modern electronic devices. Therefore, we optimized the performance of the dielectric layers by using multiple metal oxides. We combined zirconia, yttria, magnesium oxide, alumina, and hafnium oxide with the solution method to find the best combination of these five metal oxides. The physical properties of the multi-component films were measured by atomic force microscopy (AFM), ultraviolet-visible spectrophotometer, and other instruments. The results show that the films prepared by multi-component metal oxides have good transmittance and low roughness. The thicknesses of all films in our experiment are less than 100 nm. Then, metal–insulator–metal (MIM) devices were fabricated. In addition, we characterized the electrical properties of MIM devices. We find that multi-component oxide films can achieve good performances in several aspects. The aluminum-magnesium-yttrium-zirconium-oxide (AMYZOx) group of 0.6 M has the lowest leakage current density, which is 5.03 × 10−8 A/cm2 @ 1.0 MV/cm. The hafnium-magnesium-yttrium-zirconium-oxide (HMYZOx) group of 0.8 M has a maximum capacitance density of 208 nF/cm2. The films with a small thickness and a high capacitance density are very conducive to high integration. Therefore, we believe that multi-component films have potential in the process of dielectric layers and great application prospects in highly integrated electronic devices.

Gate-controlled transport in GaN nanowire devices with high- k Si 3N 4 gate dielectrics

Amorphous metal oxide has been a popular choice for thin film material in recent years due to its high uniformity. The dielectric layer is one of the core materials of the thin film transistor (TFT), and it affects the ability of charges storage in TFT. There is a conflict between a high relative dielectric constant and a wide band gap, so we solved this problem by using multiple metals to increase the entropy of the system. In this paper, we prepared zirconium-yttrium-aluminum-magnesium-oxide (ZYAMO) dielectric layers with a high relative dielectric constant using the solution method. The basic properties of ZYAMO films were measured by an atomic force microscope (AFM), an ultraviolet-visible spectrophotometer (UV-VIS), etc. It was observed that ZYAMO thin films had a larger optical band when the annealing temperature increased. Then, metal-insulator-metal (MIM) devices were fabricated to measure the electrical properties. We found that the leakage current density of the device is relatively lower and the ZYAMO thin film had a higher relative dielectric constant as the concentration went up. Finally, it reached a high relative dielectric constant of 56.09, while the leakage current density was no higher than 1.63 × 10−6 A/cm2@ 0.5 MV/cm at 1.0 M and 400 °C. Therefore, the amorphous ZYAMO thin films has a great application in the field of high permittivity request devices in the future.