Iris image quality assessment based on FPGA coprocessor

Iris recognition technology is one of the most promising biological recognition technologies now. In order to ensure the efficiency and accuracy of recognition algorithm, we need to evaluate the quality of iris images. Five indexes are used to evaluate the iris images. These indexes are eyelid occlusion, living, definition, eyelashes occlusion and cosmetic contact lenses respectively. In this way, the poor quality of images will be removed, and the rest of images will be located and segmented. Experiment results show that the proposed method can accurately eliminate the poor quality of images. This result is consistent with the subjective evaluation. After image quality evaluation, the iris images will be located and segmented accurately. It is almost 100%.

Motion estimation in videos is a computationally intensive process. A popular strategy for dealing with such a high processing load is to accelerate algorithms with dedicated hardware such as graphic processor units (GPU), field programmable gate arrays (FPGA), and digital signal processors (DSP). Previous approaches addressed the problem using accelerators together with a general purpose processor, such as acorn RISC machines (ARM). In this work, we present a co-processing architecture using FPGA and DSP. A portable platform for motion estimation based on sparse feature point detection and tracking is developed for real-time embedded systems and smart video sensors applications. A Harris corner detection IP core is designed with a customized fine grain pipeline on a Virtex-4 FPGA. The detected feature points are then tracked using the Lucas---Kanade algorithm in a DSP that acts as a co-processor for the FPGA. The hybrid system offers a throughput of 160 frames per second (fps) for VGA image resolution. We have also tested the benefits of our proposed solution (FPGA + DSP) in comparison with two other traditional architectures and co-processing strategies: hybrid ARM + DSP and DSP only. The proposed FPGA + DSP system offers a speedup of about 20 times and 3 times over ARM + DSP and DSP only configurations, respectively. A comparison of the Harris feature detection algorithm performance between different embedded processors (DSP, ARM, and FPGA) reveals that the DSP offers the best performance when scaling up from QVGA to VGA resolutions.

The ability to identify individuals based on their iris is known as iris recognition. Over the past decade iris recognition has garnered much attention because of its strong performance in comparison with other mainstream biometrics such as fingerprint and face recognition. Performance of iris recognition systems is driven by application scenario requirements. Standoff distance, subject cooperation, underlying optics, and illumination are a few examples of these requirements which dictate the nature of images an iris recognition system has to process. Traditional iris recognition systems, dubbed "stop and stare", operate under highly constrained conditions. This ensures that the captured image is of sufficient quality so that the success of subsequent processing stages, segmentation, encoding, and matching are not compromised. When acquisition constraints are relaxed, such as for surveillance or iris on the move, the fidelity of subsequent processing steps lessens.;In this dissertation we propose a multi-faceted framework for mitigating the difficulties associated with non-ideal iris. We develop and investigate a comprehensive iris image quality metric that is predictive of iris matching performance. The metric is composed of photometric measures such as defocus, motion blur, and illumination, but also contains domain specific measures such as occlusion, and gaze angle. These measures are then combined through a fusion rule based on Dempster-Shafer theory. Related to iris segmentation, which is arguably one of the most important tasks in iris recognition, we develop metrics which are used to evaluate the precision of the pupil and iris boundaries. Furthermore, we illustrate three methods which take advantage of the proposed segmentation metrics for rectifying incorrect segmentation boundaries. Finally, we look at the issue of iris image interoperability and demonstrate that techniques from the field of hardware fingerprinting can be utilized to improve iris matching performance when images captured from distinct sensors are involved.

In this paper a real time approach to reduce speckle noise and enhance structures in speckle corrupted ultrasound image is proposed. It utilizes nonlinear anisotropic diffusion for speckle removal and edge enhancement. Unlike the conventional anisotropic diffusion performed in four different directions, here diffusion is performed in eight different directions. The algorithm has been proficiently implemented using a low cost Texas Instruments (TI) Digital Signal Processor (DSP) of series TMS320C64x+. The approach speeds up the computation by utilizing the ability of Very Long Instruction Word (VLIW) processor to perform multiple operations in parallel. In addition, a new feature to select a Speckle Reduction Imaging (SRI) mode is introduced which facilitates different degree of smoothing depending on the requirement. The experimental results show that with an speckled input image of size 640 × 480 the algorithm is capable of supporting 105 frames per second (fps). This method also promises better image quality than window based filtering techniques [1]–[4].

This thesis aims to develop an embedded image processing board, which can be used to realize various image feature extraction and processing algorithms for robotic applications. The circuitry of this image board can be divided into two parts, one is for a digital signal processor (DSP) and the other for a field programmable gate array (FPGA). A low power, small size CMOS image sensor with YUV4:2:2 image format and 512x480 pixel size is adopted for image acquisition. The DSP module is mainly used for implementing image processing algorithms, while the FPGA module for lower level image processing and sensor control functions. In this work, the TMS320C6414TGLZ7 DSP from Texas Instruments Corporation and the EP2C35F672C6 FPGA from Altera Corporation were selected for the image board. In this work, speeded-up robust features (SURF) algorithm has been successfully realized on the developed image board. An USB interface with average throughput of 22MB/sec works to transfer acquired image frames and extracted SURF descriptors to a personal computer, where feature matching is executed. Experimental results show that the refresh period of frame grabbing is about 33.5ms. When the number of SURF descriptor is equal to 64, the computing time is about 417.5ms; when the number of SURF descriptor is equal to 199, the computing time is about 985ms. The typical matching rate varies from 70.2% to 20%, depending on the threshold of the patterns used in feature extraction.

This book focuses on embedded image processing and, more specifically, on the efficient implementation of image processing algorithms on the TMS320C6000 family of digital signal processors (DSPs) from Texas Instruments (TI). The text is divided into six chapters: "Introduction," "Tools," "Spatial Processing Techniques," "Image Filtering," "Edge Detection and Segmentation," and "Wavelets." The text is supported by two appendices, as well as a CD-ROM. The CD-ROM includes all source code and project files as well as many test images and one text video clip. There is no better way to learn than by example, and the book offers plenty of them. While the book is intended for signal and image processing practitioners or software developers that plan to use a TI DSP, most of the programming techniques demonstrated in the book can easily be applied to other embedded platforms. The book is well written and succeeds in filling a big void in image processing literature, tackling how to efficiently implement signal and image processing algorithms using embedded processors.

Field Programmable Gate Arrays (FPGAs) have gained popularity because their reconfigurability can speed up development and verification with relatively low cost. However the deep level of understanding required on hardware logic programming has discouraged many software engineers. An interface between host devices and FPGAs to enable designing and programming FPGAs using a software programming standard and encapsulating hardware details is much desired. In this paper we evaluate leveraging Open Computing Language (OpenCL) to rapidly design FPGAs, considering both hardware logic utilization efficiency and computing performance. On a heterogeneous computer system consisting of ARM processors and Altera FPGA, we execute an OpenCL host program on the ARM processors and an OpenCL kernel on the FPGA, to compute a parametrizable two-dimensional Mandelbrot fractal. We explore three design aspects of adjusting OpenCL work-group size, coalescing memory access, and replicating compute units to improve the FPGA computation performance. After optimizing the core algorithm, we efficiently reduced the logic utilization and Digital Signal Processing (DSP) blocks required for a single compute unit, and successfully increased the number of replicated compute units from four to six, thus delivering a 1.5X increase of parallel computation capacity of the FPGA, and improving the computing speed by 1.5X and memory bandwidth by 1.7X.

During the image acquisition procedure of an automatic iris recognition system, the iris image with low quality may lead to the personal identification failure in some cases. Therefore it is very important to adopt the image quality evaluation procedure before the image processing. In this paper, we proposed a fast image quality evaluation method based on weighted information entropy combining iris image segmentation through localization. Through this method, we can fast grade the images and pick out the high quality iris images from the video sequence captured by the image acquisition device. Experimental results show that this method can quickly and effectively screen out appropriate images to meet the requirements of the iris recognition algorithm. It can also improve the speed and accuracy of the iris recognition system.

Innovation Partners proposed and successfully demonstrated in this SBIR Phase I grant a software/hardware co-design approach to reduce both the difficulty and time to implement Field Programmable Gate Array (FPGA) solutions to data acquisition and specialized computational applications. FPGAs can require excessive time for programming and require specialized knowledge that will be greatly reduced by the company's solution. Not only are FPGAs ideal for DAQ and embedded solutions, they can also be the best solution to specialized signal processing to replace Digital Signal Processors (DSPs). By allowing FPGA programming to be done in C with the equivalent of a simple compilation, algorithm changes and improvements can be implemented decreasing the life-cycle costs and allow subsitution of new FPGA designs staying above the technological details.

Current legislation in European countries, as well as in other parts of the world, is putting stricter limits on pollutant emissions from road vehicles. This issue, in conjunction with the increase awareness of consumer for the environmental problems, will require the development of new clean propulsion systems in disruption with the current mobility solutions based on internal combustion engine. Electric, hybrid and fuel-cells vehicles (Chan, 2007) are now recognized as an indispensable mean to meet the challenges associated with sustainable mobility of people and goods. In this paradigm shift, the electric motor (EM) will assume a key role in the propulsion of future vehicles and, unlike vehicles based on internal combustion engines, the high energy and power densities will facilitate the development of new powertrains configurations. In particular, multi-motor configurations, where several EMs are allocated to each driven wheel of the vehicle, represent an attractive configuration for electric vehicles (EVs), due to the independent wheel torque control and the elimination of somemechanical systems, like the differential. These features, allied with the fast dynamics of EMs, are being explored to increase the vehicle maneuverability and safety (Geng et al., 2009) and improve the performance of the EV traction system (Hori, 2004). To cope with this rise in functional and computational complexity that current (and future) EVs require, in this work we explore the new Field-programmable Gate Array (FPGA) platform to address the powertrain control, i.e. involving the electric motor and the power converters control, of multi-motor EVs. In the past two decades, motor control applications have been dominated by software based solutions implemented in DSPs (Digital Signal Processors), due to the low cost and ease of programming (Cecati, 1999). However, these DSP solutions are facing increasing difficulties to respond to the ever-increasing computational, functional and timing specifications that modern industrial and vehicular applications require (Monmasson & Cirstea, 2007). For instance, when single-coreDSP based solutions needs to incorporate complex and time-critical functions, e.g. multi-motor control, the sequential processing of this approach decrease the controller bandwidth (see Fig. 1), which may compromise the application timing specification. Multi-core DSPs are a possible alternative to address this concern, but they also add costs and interconnection complexity. Consequently, in the last years, FPGAs received an increased interest by the academy and industry as an option to offload time-critical tasks from the DSPs (Lopez et al., 2008; Rahul et al., 2007; Ying-Yu & Hau-Jean, 1997), or even replace the DSPs control platform by a System on Chip (SOC) based on FPGAs (Idkhajine et al., 2009). 7

We present recent results of a performance benchmark of selected low-level vision algorithms implemented on different high-speed embedded platforms. The algorithms were implemented on a digital signal processor (DSP) (Texas Instruments TMS320C6414), a field-programmable gate array (FPGA) (Altera Stratix-I and II families) as well as on a mobile PC processor (Intel Mobile Core 2 Duo T7200). These implementations are evaluated, compared, and discussed in detail. The DSP and the mobile PC implementations, both making heavy use of processor-specific acceleration techniques (intrinsics and resource optimized slicing direct memory access on DSPs or Intel integrated performance primitives Library on mobile PC processors), outperform the FPGA implementations, but at the cost of spending all its resources to these tasks. FPGAs, however, are very well suited to algorithms that benefit from parallel execution.

The drives of power amplifiers of magnetic levitation servo spindle applied to micro EDM (Electron discharge machining) based on FPGA (Field programmable gate array) are developed. The drive module that produces the PWM (Pulse width modulation) waves that conform to the requirements of spindle power amplifiers involving three-level half bridge switch power amplifier, three-level full bridge switch power amplifier and motor power amplifier, according to input of action values from magnetic levitation servo spindle controller DSP (Digital signal processor) is designed. Multi-PWM producing algorithm by single timer with multi comparing nodes is proposed. After being applied to control system of magnetic levitation servo spindle, the drives accomplish conversion from DSP action values to PWM waves. The PWMs that drive radial coil current power amplifier have phase difference of 180°. The PWMs that drive axial coil current power amplifier have dead zone time and their wave shapes are complementary. The PWMs that drive the motor power amplifier conform to requirements of power amplifier chip LMD18200. Using FPGA to realize the drive function of spindle power amplifier makes the drive design more flexible, resource distribution of DSP more optimized, the task of algorithms running more centralized, and the drives module gets simpler and more reliable because the phase shift circuit and dead zone circuit are cancelled but the function of phase shift and dead zone is reserved.

In this paper, a new motion control hardware architecture is proposed for improved motion performance of robotic manipulators during high speed motion. The main idea is to remove the servo control loop from the DSP (digital signal processor) to a FPGA (field programmable gate array), and utilize the high speed hardwired logic of the FPGA to enhance the computation capability and relieve the computing load on the DSP. The control algorithm is partitioned into a linear portion and a nonlinear portion. The linear portion with position/velocity feedback represents the major control loop and is implemented in the FPGA. The nonlinear portion acts as dynamic compensation to the linear portion to perform complex modeling related calculations, and is implemented in the DSP. A new FPGA-based motion control IC is designed to realize this new control hardware structure. Experiments were conducted on a Yamaha robot manipulator to compare new control architecture and the existing one, when the same control algorithm was used. Experimental results demonstrate that the proposed new control architecture exhibits much improved motion performance especially during high-speed motions

In this paper, we describe the multiple biometric recognition system based on 32 bit floating-point digital signal processor (DSP) and field programmable gates array (FPGA). In addition, it has the function of real-time display, which can help the users easily capture the perfect image that they need. Different from other platforms of using DSP and FPGA, we have two kinds of parallel bus interfaces between them, the EMIF and HPI interface. With the help of the Hardware Description Language (HDL) Verilog HDL, we make it true that the DPS and FPGA can co-process the matching algorithms. Comparing with the matching time that processes only by the DSP, the co-processing is more efficient than the processing only by one processor. Besides, we leave several parallel and series interfaces in our board for the future use. Therefore, our system can be applied to many different digital signal processing domains and provide them an excellent computing platform.

This work presents the hardware and software architecture for the detection of fractures and edges in materials. While the detection method is based on the novel concept of Low Transient Pulse (LTP), the overall system implementation utilizes two microelectronics technologies: Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA). The DSP carries out the analysis of the received signal at a much lower rate hence can accommodate a large number of signal channels. The FPGA runs at a higher frequency (62.5MHz) to generate the LTP signal and to calculate the envelope of the received signal (sampled at 1MHz). This research elaborates on designing a Quadrature AM (QAM) demodulator on the FPGA for the received signal from the ultrasound and for the detection of the presence of edges/fracture on the test materials. The complete system is designed and optimized in a high level Matlab\Simulink fixed point simulation. Different sub-blocks are then implemented and optimized on the FPGA where efforts are taken to maintain its accuracy with the simulated model. In this work, the technology is applied to determine the location of the Sawbone plate edges based on the received signals which are then passed through a QAM demodulator in the FPGA and a peak detector in the DSP to calculate the echo peak times.