Irreducible Polynomials: Non-Binary Fields

The paper concerns Low Density Parity Check (LDPC) codes over nonbinary Galois Fields GF(q), that are a generalization of the industrial standard binary LDPC codes for forward error correction in communication and information systems. The semi-regular nonbinary LDPC codes can outperform their binary counterparts in the case of short to moderate code word lengths. The methods for the good code construction based on a computer search techniques are already well investigated. However, there is a lack of systematic results for optimal weight distribution of columns of parity check matrices for codes over different field order and different rate. In this article we present a Monte Carlo like algorithm for column weight optimization devoted to nonbinary semi-regular codes along with optimization results that facilitate the codes construction computer-based methods.

In Japan, the next generation of Integrated Services Digital Broadcasting — Terrestrial (ISDB-T) system is being developed for transmission of large-volume content services such as ultra high definition television (UHDTV). The system uses low density parity check (LDPC) code as the forward error correction (FEC) to improve its robustness. In particular, the performance of the system's FEC should be evaluated not only in additive white Gaussian noise (AWGN) environments, but also in multipath environments. Moreover, it would be desirable for the new FEC to have better performance than the previous one even in multipath environments. Previous research evaluated the transmission performance of LDPC code by using computer simulations of the propagation model. The actual propagation characteristics were not evaluated. In this paper, we describe the transmission performance of convolutional coded orthogonal frequency division multiplexing (CC-OFDM) and LDPC coded OFDM (LDPC-OFDM) in computer simulations using the same OFDM frame structure and propagation channels as measured in an outdoor experiment conducted in an urban area. We show that LDPC code outperforms CC in multipath environments and how the transmission performance depends on the code rate. In addition, we analyze the correlation between transmission performance and propagation channels.

RS (Reed - Solomon) code is used in DVB-H (digital video broadcasting - handheld) system as an addtional error correcting code to improve the performance during mobile reception. LDPC (low density parity check) code which is rediscovered recently shows the astonishing performance. Therefore LDPC code can be used to replace RS code in order to improve the performance further since both of them are block codes. So the performance of LDPC code in MPE-FEC (multi protocol encapsulation - forward error correction) frame of DVB-H system is analyzed in this paper.

Forward Error Correction is a technique which is used to correct the modified data when transmitted over a noisy channel. Forward Error correcting codes detect and correct errors with decoders. In this paper Error Recovery Algorithm is proposed which combines the Bezier curves over Galois Field GF (p⁁m) and the Low Density Parity Check Codes to generate non-binary codeword. The proposed decoder is capable of detecting and correcting the modified image. When binary representation is used for Galois field elements, the Error Correction can be achieved by performing modular addition over Galois Field. The hardware complexity reduces to XOR gates. This enhances the speed of the decoder as there is no generation and propagation of carry during Galois field addition.

PMD mitigation through interleaving LDPC codes with polarization scramblers

Turbo codes are attractive compared with Low Density Parity Check (LDPC) codes for Forward Error Correction (FEC) applications mainly due to their superior performance, especially at low Signal-to-Noise Ratio (SNR) such as are common in Powerline channels. For example, IEEE 1901-FFT PHY used the Turbo coding scheme defined in the HomePlug AV standards. However, patent fees are usually required for each turbo-code enabled manufactured device. The objective of this paper is to examine whether unlicensed LDPC codes, with optimized choices of block lengths, could be a viable alternative for future Powerline Communications (PLC) applications. The paper shows that the performance of the LDPC codes can approximate that of the Turbo codes with higher block lengths, on channels with typical and realistic PLC characteristics. The paper also shows that the additional complexity associated with this increase in block length can be mitigated by the use of Quasi-Cyclic LDPC (QC-LDPC) codes.

Digital Video Broadcasting-Terrestrial second generation (DVB-T2) systems are increasingly deployed for high quality terrestrial broadcasting. However, low Signal-to-Noise Ratio (SNR) conditions in urban and fringe coverage areas pose significant challenges, resulting in elevated Bit Error Rates (BER) and degraded service reliability. Forward Error Correction (FEC) techniques, particularly Low-Density Parity-Check (LDPC) and Bose Chaudhuri Hocquenghem (BCH) codes, play a crucial role in mitigating transmission errors and ensuring robust communication. This study investigates a systematic approach to optimizing LDPC and BCH FEC schemes to enhance transmission reliability and minimize BER under low-SNR conditions in DVB-T2 networks. Using simulation-based analyses, the study evaluates multiple LDPC code rates (e.g., 1/2, 2/3, 3/4) in combination with BCH codeword lengths and error-correcting capabilities. Results indicate that an optimized LDPC (64800, 32400) configuration combined with a BCH (255, 239) code significantly reduces BER, achieving approximately 10⁻⁵ at an SNR of 2 dB, compared to a BER of 10⁻³ using standard DVB-T2 FEC configurations. Additionally, iterative decoding algorithms for LDPC were fine-tuned to balance convergence speed and error correction performance, demonstrating a 25% reduction in decoding iterations without compromising reliability. The analysis also explores trade-offs between redundancy, throughput and latency, highlighting the practical considerations for real-world deployment. The findings underscore that strategic optimization of LDPC/BCH FEC parameters is critical for maintaining broadcast quality in low-SNR scenarios. By enhancing error resilience and reducing BER, the proposed approach improves signal integrity, supports consistent reception in fringe areas and maximizes spectrum efficiency. This work provides a foundation for adaptive FEC strategies in future DVB T2 systems, enabling broadcasters to deliver reliable high-definition content even under challenging channel conditions.

Forward error correction is an essential part of digital communication systems. Non-binary low-density parity-check (NB-LDPC) codes have an excellent communications performance for short block lengths. The higher the field size is, the better the communications performance is. Non-binary LDPC codes can outperform all other state-of-the-art code classes. However, the algorithmic decoding complexity grows with the field size. For an intended, future use of these codes in real systems, an efficient hardware implementation is mandatory. Hardware architectures for binary LDPC codes are well investigated, but efficient implementation of non-binary LDPC decoders is still an open field. To the best of our knowledge, this paper studies for the first time the hardware implementation costs for non-binary LDPC decoders with Galois field sizes of 4, 16 and 256 on FPGA and a 65nm ASIC technology.

In this paper, we study two problems of providing reliable data transmission and developing aggregation techniques for correlated data in wireless sensor networks. A system with forward error correction (FEC) can provide an objective reliability while using less transmission power than a system without FEC. Because of the additional parity bits and encoding/decoding energy consumptions, we study the effect of FEC on energy efficiency. We propose to use LDPC codes for FEC. We show that wireless sensor networks using LDPC codes are almost 45% more energy efficient than those that use BCH codes, which were shown to be 15% more energy efficient than the best performing convolutional codes. Then we study the problem of providing aggregation for two and three correlated nodes in wireless sensor networks. We propose to use LDPC codes in wireless sensor networks for source and channel coding to obtain a two-fold energy savings. For two correlated nodes, we study both distributed source coding and joint source-channel coding. While distributed source coding using LDPC codes was studied before, joint source-channel coding using LDPC codes is introduced for the first time. The difference between our work in distributed source coding using LDPC codes and the previous work lies in the LDPC code design procedure. The simulation results show that our proposed design criteria improves the performance of the source coding. The convergence of the non-uniform LDPC code of our design technique is almost 60% closer to the Slepian-Wolf limit. For three correlated nodes, we study distributed source coding using LDPC codes. We simplified the problem of design procedure to randomly punctured LDPC codes. This is a new approach for designing LDPC codes and the simulation results for code of length 1000 shows that the convergence of the LDPC code is achieved at compression rate 0.3174 which is only 0.08 away from the Slepian-Wolf limit.

Low Density Parity Check (LDPC) codes have capacity-approaching performance over several channels of interest. In practice, for good block-error rate performance, the girth of the Tanner graph of an LDPC code needs to be as high as possible. In theory, to show that block-error rate approaches zero for increasing block-lengths, the girth of the Tanner graph sequence needs to tend to infinity with block-length. To meet these requirements, we construct sequences of large-girth irregular LDPC codes for a given degree-distribution pair (DDP) by applying a general node splitting algorithm on large girth graphs. The obtained Tanner graph meets the required DDP up to a suitable approximation. By optimizing the node-splitting method and using suitable large-girth graphs, we show code constructions with smaller block length for the same girth, when compared to previous constructions. Similar gains in block length are observed in the construction of sequences of large-girth protograph LDPC codes. Simulations, over a binary erasure channel, confirm the gains in block-error rate obtained by the large girth construction.

Big data storage demands larger cluster. The increasing size of the cluster may lead to failures of larger number of nodes. To provide reliable big data storage, replications are not cost-effective and does not provide a robust solution to prevent data loss. Traditional erasure codes applied in the RAID system such as Reed-Solomon (R-S) based solutions have limitations in providing high reliability. This is because higher reliability requires erasure codes with larger size. The computational cost of the R-S codes increase quadratically with the number of failures the R-S codes can tolerate for the same redundancy rate. It has been shown that Low Density Parity Check (LDPC) codes have lower computational cost and repair network traffic compared with R-S based solutions. Unfortunately, there does not exist a construction method for LDPC codes with larger size to control the computational cost and repair traffic. In this paper, a novel method is proposed to construct a family of LDPC codes - expanCodes with expandable sizes. The proposed expanCodes allows the encoding and decoding complexity remain unchanged with the increase of the size of the LDPC codes. As a result, increased reliability can be achieved without additional computation and repair traffic. The proposed expanCodes is integrated with the Hadoop system. Simulations show that more than 29% decrease in terms of encoding and decoding latency compared with R-S based solutions.

This letter gives a random construction for Low Density Parity Check (LDPC) codes, which uses an iterative algorithm to avoid short cycles in the Tanner graph. The construction method has great flexible choice in LDPC code’s parameters including codelength, code rate, the least girth of the graph, the weight of column and row in the parity check matrix. The method can be applied to the irregular LDPC codes and strict regular LDPC codes. Systemic codes have many applications in digital communication, so this letter proposes a construction of the generator matrix of systemic LDPC codes from the parity check matrix. Simulations show that the method performs well with iterative decoding.

Low Density Parity Check (LDPC) are the linear error correction codes for amendment of mistakes, a technique of transmitting the messages over the noisy channel. With lieu- Shannon’s controlled implementation and typically parallel execution of plan, low-density parity check codes are mainly executed at enquire and well-designed area of applications. Bipartite graph is used for development of LDPC codes. LDPC being limit stirring in the direction of codes which means its actual building exists that enables outer edge to be closely intended for symmetry of a channel with no memory. FPGA or Field Programmable Gate Array is based on configurable logic block (CLB) and is a semiconductor gadget that is associated by virtue of programmable interconnects. FPGAs are highly robust and can be created or designed as per the application or usefulness prerequisite of application. This research paper presents adaptable and more compatible LDPC decoder in change for other general LDPC decoder. This decoder has a completely adaptable LDPC plan in FPGA, which supports distinct codes and rate of information. The design is implemented in Xilinx ISE 14.2 software using VHDL programming and synthesized on SPARTAN 3E FPGA. Keywords: Sparse bipartite graph, threshold, Shannon limit, Very High Speed Integrated Circuit Hardware Description Language (VHDL) Cite this Article Sachit Gupta, Richa, Adesh Kumar. FPGA Implementation of LDPC Codes. Journal of Telecommunication, Switching Systems and Networks . 2018; 5(1): 21–28p.

Low-density Parity check codes (LDPC) are gaining interest for high data rate application in both terrestrial and spatial communications which requires low bit error rate. This paper proposes an algorithm through which the best parity check matrix is obtained for irregular low density parity check codes, which reduces the Bit Error Rate ,Frame Error Rate and computational complexity. Tanner graph also called a bipartite graph format in an Low Density Parity Check (LDPC) code design contains many short cycles; it will produce a computational complexity in a code design process and it degrades the code performance. To overcome this effect, we proposed an new algorithm which obtains a best final parity check matrix. Throughout the paper we will give the detailed description of an efficient algorithm proposed. The complexity is studied graphically and analytically. Using proposed algorithm, cycles of length four observed in corresponding matrix are removed. Each matrix is evaluated over a noisy Additive White Gaussian Noise (AWGN) channel. Bit Error rate and Frame error rate is calculated. The results are compared with randomly generated best parity check matrix. Simulation results shows that proposed method successfully overcomes the computational complexity and meets the near Shannon limit.

Scheduling strategy is considered an important aspect of belief-propagation (BP) decoding of low-density parity-check (LDPC) codes because it affects the decoder's convergence rate, decoding complexity and error-correction performance. In this paper, we propose two new scheduling strategies for the BP decoding of non-binary LDPC (NB-LDPC) codes. Both the strategies are devised based on the concept of check node reliability and employ a heuristically defined threshold which can adapt to the communication channel variations. As the scheduling strategies only update a subset of the check nodes in each iteration, they result in reduced iteration cost. Furthermore, since the BP performs suboptimally for finite-length LDPC codes, especially for short-length LDPC codes, by enhancing the message propagation over the Tanner Graphs of short-length NB-LDPC codes, the new scheduling strategies can even improve the error-correction performances of BP decoding. Simulation results demonstrate that the new scheduling strategies provide good performance/complexity tradeoffs.