Java components with constraints and preferences in automatic administration of execution and placement

In February 2000 the NESSIE project has launched an open call for the next generation of cryptographic algorithms. These algorithms should offer a higher security and/or confidence level than existing ones, and should be better suited for the constraints of future hardware and software environments. The NESSIE project has received 39 algorithms, many of these from major players. In October 2001, the project completed the first phase of the evaluation and has selected 24 algorithms for the second phase. The goal is to recommend a complete portfolio of algorithms by the end of 2002. This article presents the status of the NESSIE project after two years.KeywordsSmart CardBlock CipherAdvance Encryption StandardStream CipherCryptographic AlgorithmThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Virtualization technology has been widely applied in data centers and IT infrastructures, with advantages of server consolidation and live migration. Through live migration, data centers could flexibly move virtual machines among different physical machines to balance workloads, reduce energy consumption and enhance service availability.Today's data centers can grow to a huge scale. This implies that frequent live migration would be desirable for the economic use of hardware resources. Then, the performance of the live migration strategy will be an issue. So, we need a reliant evaluation method to choose the software and hardware environments that will produce the best live migration performance.However, there is not a complete live migration benchmark available currently. In addition, the existing evaluation methodologies select different metrics, different workloads and different test means. Thus, it is difficult to compare their results.In this paper we first survey the current research and their evaluation methods on live migration. We then summarize the critical issues for the live migration evaluation and also raise other unreported potential problems.We propose our solutions and present an implementation in our live migration benchmark -- Virt-LM. This is a benchmark for comparing live migration performance among different software and hardware environments in a data center scenario. We detail its design and provide some experimental results to validate its effectiveness.

TUIO is an open framework that defines a common protocol and API for tangible- and multitouch-surfaces. The protocol is based on Open Sound Control and allows the platform-independent encoding and transmission of an abstract description of interactive surfaces, including touch events and tangible object states. While the original TUIO specification has been implemented for various hardware and software environments, there are not as many feature complete reference implementations of the next TUIO generation, although its specification [2] has been finalized and partially implemented by community members. The TUIO Hackathon at the International Conference for Interactive Tabletops and Surfaces is addressing expert users and developers of hardware and software environments for surface-based tangible user interfaces that are interested in experimenting with this new framework, with the goal of initiating the development and integration of new TUIO implementations.

As an efficient technique to accelerate system-on-chip (SoC) design, software/hardware co-simulation gives a flexible method to simulate hardware and software simultaneously and save the time-to-market. In this paper, a platform of software/hardware co-simulation is implemented, which utilize a debugger to interconnect the server and the design under test (DUT) on remote FPGA board via Internet. The software environment and hardware environment are run on the server and remote FPGA board respectively. The debugger establishes a real-time bidirectional data path between them and performs the data conversion. The embedded interface module can be synthesized with user's DUT smoothly. This platform takes full advantage of software's flexibility and hardware's high speed, supports remote operation and various types of co-simulation modes, while consumes few hardware resource.

We propose a system to facilitate biology communication by developing a pipeline to support the instructional visualization of heterogeneous biological data on heterogeneous user-devices. Discoveries and concepts in biology are typically summarized with illustrations assembled manually from the interpretation and application of heterogenous data. The creation of such illustrations is time consuming, which makes it incompatible with frequent updates to the measured data as new discoveries are made. Illustrations are typically non-interactive, and when an illustration is updated, it still has to reach the user. Our system is designed to overcome these three obstacles. It supports the integration of heterogeneous datasets, reflecting the knowledge that is gained from different data sources in biology. After pre-processing the datasets, the system transforms them into visual representations as inspired by scientific illustrations. As opposed to traditional scientific illustration these representations are generated in real-time - they are interactive. The code generating the visualizations can be embedded in various software environments. To demonstrate this, we implemented both a desktop application and a remote-rendering server in which the pipeline is embedded. The remote-rendering server supports multi-threaded rendering and it is able to handle multiple users simultaneously. This scalability to different hardware environments, including multi-GPU setups, makes our system useful for efficient public dissemination of biological discoveries.

Since the Keccak algorithm was selected by the US National Institute of Standards and Technology (NIST) as the standard SHA-3 hash algorithm for replacing the currently used SHA-2 algorithm in 2015, various optimization methods have been studied in parallel and hardware environments. However, in a software environment, the SHA-3 algorithm is much slower than the existing SHA-2 family; therefore, the use of the SHA-3 algorithm is low in a limited environment using embedded devices such as a Wireless Sensor Networks (WSN) enviornment. In this article, we propose a software optimization method that can be used generally to break through the speed limit of SHA-3. We combine the θ, π, and ρ processes into one, reducing memory access to the internal state more efficiently than conventional software methods. In addition, we present a new SHA-3 implementation for the proposed method in the most constrained environment, the 8-bit AVR microcontroller. This new implementation method, which we call the chaining optimization methodology, implicitly performs the π process of the f-function while minimizing memory access to the internal state of SHA-3. Through this, it achieves up to 26.1% performance improvement compared to the previous implementation in an AVR microcontroller and reduces the performance gap with the SHA-2 family to the maximum. Finally, we apply our SHA-3 implementation in Hash_Deterministic Random Bit Generator (Hash_DRBG), one of the upper algorithms of a hash function, to prove the applicability of our chaining optimization methodology on 8-bit AVR MCUs.

Software environment: The source code is written in Fortran77. The executable file is compiled for the protected DOS mode (32 bits), Windows 3.1x (using Win32S), Windows 95 and Windows NT. The program offers a user-friendly graphical user interface (GUI) that is fully mouse-controlled. The graphical interface is based on the INTERACTER Library version 4.0. Hardware environment: The program runs on PC-compatible computers under DOS 6.0 or higher, Windows 3.1x (with Win32S), Windows 95 and Windows NT. The DOS version needs about 2.0 Mbytes of disk space (the program is bounded with the DOS-Extender) and 1.2 Mbytes for the other versions. The program uses VGA/SVGA graphics and needs an IBM-compatible mouse. Program specification: Up to about 100 atoms in the asymmetric unit can be used to calculate the contour maps of the bond-valence sum. The program found the higher graphics resolution for DOS and for Windows it needs a Windows video driver with colours 32 k/65 k/ 16 M. There are two forms of output file: HPGL and PostScript. In DOS one can choose a Laserjet or Deskjet printer. Documentation: The program is very easy to use, but a manual is provided in the form of a MS-Word document, with some examples. Availability: VALMAP 1.0 can be freely obtained from the authors by e-mail (jplatas@ull.es).

Digital certificates provided by PKI are commonly used for identification and authentication services. The corresponding private key can be protected by USB keys, TEE/SE, etc., in the hardware environment. But in the software environment, the private key is relatively easy for an attacker to steal. This paper presents the design and implementation of a collaboration public key services system for mobile applications, which is named MC-PKS. The MC-PKS system provides a set of mobile digital certificate signatures and decryption schemes for PKI in the form of APP-server collaboration. It protects the private key utilizing information hiding and secret splitting on two-party signature schemes, which ensures that the split private key which has been split can still generate a digital signature if and only if with the cooperation of the server. We then analyze the security of the proposed system and show that it satisfies all known security requirements in practical applications. The performance analysis demonstrates that the MC-PKS system also achieves the resource-constrained requirements of mobile applications.

A review of Timothy M. O'Brien's "Jakarta Commons Cookbook"

Electronic total stations and data collectors have come to be recognized as vital productivity tools in the age of digital mapping. Information encoded in data collectors represents the first and, perhaps, most important link in the information chain from field data collection to data presentation and data management. Unfortunately, data collectors today have largely been designed to function well within a user‐ or manufacturer‐defined hardware and software environment. Outside the designed environment, the efficacy of most data collectors deteriorates because of their inability to cooperate fully with other hardware and software systems. This paper proposes the standardization of a neutral‐file fomat, initial data collector exhange format (IDCXF), for integrating diverse data‐collector systems. The concept of entity coding for point‐line features in the context of CAD/GIS mapping is also proposed for examination.

This paper reports on the programming environment we developed for blind APL-programmers. We defined a Braille-APL-Notation and developed an APL-editor, fitting the special needs of blind programmers. Since January, 1980 the Braille-APL-Notation has been successfully used by a blind programmer in our Institute. We discuss various problems blind programmers have in communicating with a computer, and present the hardware and software environment we provided and tested in Stuttgart. Finally, we report on our experience and results.

The brief of this paper is to discuss the design and realization of precision agriculture information system based on 5S. The precision agriculture is representing the direction of agriculture development, is also the focal point of agriculture research. In this paper, the concept of precision agriculture and the features of 5S technology are briefly introduced. Then an application of 5S technology and database technology to the developing precision agriculture, and an establishment of precision agriculture information system based on 5S technology integration are proposed. The total structure, hardware and software environment, database design and function module design, realization methods of this system are also introduced.

Next generation autonomous driving functions heavily depend on various computationally intensive algorithms based on machine vision. Design and development of such algorithms is challenging, requiring engagement of a wider community and the availability of appropriate, cost-effective tooling. Setting up a hardware and software environment that would both reflect actual automotive requirements and facilitate development and prototyping, is an uneasy task. In this paper, we analyze the available development platforms which could be utilized in automotive machine vision, with specific regard to new algorithm requirements, such as the utilization of AI, hardware acceleration and low latency. We give a proposal of an affordable and scalable development setup consisting of heterogeneous, vision-enabled SoCs and automotive interfaces.

Network emulation offers real-time simulation that enables test and evaluation of real network systems, protocols, and applications in a reconfigurable and controllable hardware and software environment. Real network traffic is processed by the protocol stacks of physical systems across the entire emulation environment. Standalone emulators can only be used to test end-to-end protocols and applications; simple emulator testbeds are non-scalable due to the one-to-one mapping scheme. We present a distributed emulator cluster that can faithfully emulate large-scale wide area networks with only a considerably smaller number of workstations. In the emulator cluster, a network topology is accurately mapped to a virtual topology in which certain number of virtual nodes are properly configured and emulated. We have developed an algorithm to partition a target network such that each partition can be emulated by a physical node. The emulator cluster can emulate a variety of network conditions and traffic dynamics, as well as incorporating new protocols and models. Preliminary test results show the high scalability of emulator cluster in terms of emulation validity and accuracy with a single physical node and in the entire environment.

The last several years have witnessed a surge of activity in lightweight cryptographic design. Many lightweight block ciphers have been proposed, targeted mostly at hardware applications. Typically software performance has not been a priority, and consequently software performance for many of these algorithms is unexceptional. Simon and Speck are lightweight block cipher families developed by the U.S. National Security Agency for high performance in constrained hardware and software environments. In this paper, we discuss software performance and demonstrate how to achieve high performance implementations of Simon and Speck on the AVR family of 8-bit microcontrollers. Both ciphers compare favorably to other lightweight block ciphers on this platform. Indeed, Speck seems to have better overall performance than any existing block cipher — lightweight or not.