L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture

Encryption of data is of utmost importance for secure transmission. Traditional keyword search techniques downloading all the data and decrypting locally is clearly impractical, due to the huge amount of bandwidth cost in cloud scale systems. This paper presents a methodology for encrypting the data for limited reserved strings that are stored in Counting Bloom Filters (CBF). CBF is a small array of element addresses that are connected to the array through a hashing mechanism. Counting bloom filter is used for increasing the speed of the set membership tests. If the string is a member of counting bloom filter it is encrypted using Data Encryption Standard, else the string is transmitted without encryption. This reduces the effective time for encryption and increases security.

Bloom filters are probabilistic data structures that are popular in networking for set representation; however, they show an inherent inaccuracy due to false positives. One of the potential attacks on Bloom filters is to pollute them with elements that cause the filter to have a larger false positive probability than under normal operation; Pollution is simple when an attacker knows the details of the filter implementation. Recent research has shown that also black-box adversaries can pollute a counting Bloom filter (a common variant of the filter that also supports removals) with no knowledge of its implementation. As over time, many variants and improvements of Bloom filters have been proposed, it is of interest to study whether they can also be polluted and if so also the increase in their false positive probability. This paper first proposes and then evaluates pollution attacks for some of the most common variants including the Block Bloom filters (BBFs), the Variable Increment and Fingerprint Counting Bloom filters (VI-CBFs and FP-CBFs). The results show that with or without knowledge of the implementation, these variants of the Bloom filter are significantly more vulnerable to pollution attacks than the traditional Bloom filter. In particular, BBFs are extremely vulnerable, so providing an insight on their impact and use in practical systems when the number of memory accesses per lookup must be reduced.

We present a Linear Feedback Shift Register (LFSR) like architecture, because the LFSR can bring a lot of data by using a few bits. We calculate the ATE data by Gauss-Elimination and put the ATE data to our decompression architecture to generate a lot of patterns. And one ATE data will run several times in the architecture. If some faults cannot be detected, we will generate the patterns which are brought by fault simulation. If still a few faults cannot be detected, the faults will be caught by directly modify the bits of ATE data. The less ATE data we use, the less cycles we need. Because the reason, we can get high speed testing. And the less data, the low-cost environment we need. The cycle we can save is up to 61.60x. And the average rate of compression can get 19.33x.

Many modern applications in important application domains, as communication, image and video processing, multimedia, etc. involve much data-level parallelism (DLP). Therefore, adequate exploitation of DLP is highly relevant. This paper focuses on effective and efficient exploitation of DLP for the synthesis of vector VLIW ASIP processors. We propose analytical energy models in order to rapidly estimate the energy consumption of a nested loop executed on a VLIW ASIP with respect to different vector widths. The models perform a rapid and relatively accurate energy consumption estimation through combining the relevant information on the application and implementation technology. The analytical energy models are experimentally validated and the validation results are discussed.

Concurrent error detection and correction is an effective way to mitigate fault attacks in cryptographic hardware. Recent work on differential power analysis shows that even mathematically-secure cryptographic protocols may be vulnerable at the physical implementation level. By measuring energy consumed by a working digital circuit, it is possible to gain valuable information about the encryption algorithms used and even the specific encryption keys. Thwarting such attacks requires a new approach to logic and physical designs. This paper presents a systematic approach to fault tolerant cryptographic hardware designs. Firstly, the effectiveness of the Hamming code based error correction schemes as a fault tolerance method in stream ciphers is investigated. Coding is applied to Linear Feedback Shift Registers (LFSR) based stream cipher implementations. The method was implemented on industrial standard stream ciphers, e.g. A5/1(GSM), E0 (Bluetooth), RC4 (WEP), and W7. The performance variation of stream cipher algorithms with error detection and correction was studied by synthesising the designs on Field Programmable Logic Arrays (FPGA) and Application Specific Integrated Circuits (ASIC). Further, we analyse hardware building blocks to minimise switching activity of a circuit over all possible inputs and input transitions by adding redundant gates and increasing the overall number of signal transitions. We also discuss the overhead and compositional properties of uniformly-switching circuits.

Dynamic properties investigation of an acoustic black hole beam with dynamic vibration absorber based on analytical method

Large-scale CMPs with hundreds of cores require a directory-based protocol to maintain cache coherence. However, previously proposed coherence directories are hard to scale beyond tens of cores, requiring either excessive area or energy, complex hierarchical protocols, or inexact representations of sharer sets that increase coherence traffic and degrade performance. We present SCD, a scalable coherence directory that relies on efficient highly-associative caches (such as zcaches) to implement a single-level directory that scales to thousands of cores, tracks sharer sets exactly, and incurs negligible directory-induced invalidations. SCD scales because, unlike conventional directories, it uses a variable number of directory tags to represent sharer sets: lines with one or few sharers use a single tag, while widely shared lines use additional tags, so tags remain small as the system scales up. We show that, thanks to the efficient highly-associative array it relies on, SCD can be fully characterized using analytical models, and can be sized to guarantee a negligible number of evictions independently of the workload. We evaluate SCD using simulations of a 1024-core CMP. For the same level of coverage, we find that SCD is 13× more area-efficient than full-map sparse directories, and 2× more area-efficient and faster than hierarchical directories, while requiring a simpler protocol. Furthermore, we show that SCD's analytical models are accurate in practice.

Compiler-directed dynamic voltage scaling (DVS) is an effective low-power technique in real-time applications, where compiler inserts voltage scaling points in a real-time application, and supply voltage and clock frequency are adjusted to the relationship between the remaining time and remaining workload at each voltage scaling point. In this paper we present the analytical energy model of proportional dynamic voltage scaling in real-time applications. Using the analytical model, we theoretically prove the optimal configuration of voltage scaling points that minimizes energy consumption. Furthermore, in order to seek the optimal configuration taking into account voltage scaling overhead in the most frequent execution case, we propose a configuration methodology, where a profile-based method constructs the abstract execution pattern of an application, voltage scaling points are inserted into the abstract execution pattern by the optimal configuration without taking into account voltage scaling overhead, and then we can find the optimal configuration considering voltage scaling overhead by deleting some voltage scaling points from the execution pattern. Finally, the remaining points are inserted into the application by compiler. The simulation results show that, when taking into account voltage scaling overhead, the configuration methodology reduces energy consumption efficiently.KeywordsSupply VoltageClock FrequencyOptimal ConfigurationSlack TimeDynamic Voltage ScalingThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

In this paper, the dynamic behavior of electrostatically actuated radio frequency-microelectromechanical system (RF-MEMS) switches is analyzed using energy considerations. An analytical model for bridge-type RF-MEMS switches is proposed and the time evolution of the system total energy is calculated numerically. Switch actuation, release times, and damped release response are derived from energy analysis with focus on the effect of increasing the actuation voltage on the RF-MEMS dynamic behavior. The dynamic and RF characteristics of different RF-MEMS ohmic-contact switches have been measured using an experimental set-up based on microwave instrumentation. The measured results show a good agreement with simulations, thus validating the proposed analytical model. It is shown (theoretically and experimentally) that the damped release response increases the effective time to reach the RF/microwave OFF-state switch isolation (up to three natural periods of the mechanical system). $\hfill{[2013\hbox{-}0222]}$

Including seismic risk mitigation measures into the Levelized Cost Of Electricity in enhanced geothermal systems for optimal siting

This paper first presents an analytical interconnect energy model with consideration of event coupling, which is not considered by the conventional $\frac{1}{2}CV^2$ model. Our energy calculation algorithm has the same time complexity as the $\frac{1}{2}CV^2$ model, and is several orders of magnitude faster than {\tt HSPICE} with less than 5% error. In comparison, the error of the $\frac{1}{2}CV^2$ model can be as high as 100%.

The design and analysis of a protocol with an unbounded sequence space that ensures reliable point-to-multipoint communication over local area networks is considered. Analytical models are used to obtain throughput and delay characteristics. Simulation is used to provide an assessment of the analytical results. Salient features of the authors' approach are: (i) the responsibility of ensuring reliable message communication is vested with the receivers, (ii) receivers arbitrate in sending their retransmission requests, and (iii) an attempt is made to reduce the overall number of transmissions. The approach advocated here serves as a design step in obtaining an improved protocol that supports a finite window. >

Gas pulsations within the refrigerant gas cavity is one of the principal noise propagating paths in reciprocating compressors. This paper provide a physical insight to the relationship between the gas pulsations inside the cavity and noise radiation of reciprocating compressors. The refrigerant gas cavity of the test compressor is modeled as a space between concentric spherical shells and analyzed with modal expansion techniques. Gas pulsations within the cavity are mathematically represented as the forcing terms of the inhomogeneous wave equation in spherical coordinates. The pressure distribution inside the cavity is then estimated accordingly. Based on the orthogonality principles, the noise radiation patterns associated with the gas pulsations are predicted. Acoustic modal analysis, directivity test and running speed sensitivity test are conducted to identify the acoustic characteristics of cavity and to verify the analytical model. The experimental results are in good agreement with the prediction of the analytical model. Thus, the concentric, spherical shell model well describes the acoustic characteristics of cavity within the test compressor. This model can also be employed as a design tool to analyze the effects of system parameter variation on overall noise radiation.

Maximizing the network lifetime through balancing energy and lowering the delay is a primary design goal of wireless sensor networks (WSNs). In WSNs, the sensor nodes task is to acquire the data from the area or point of interest and transmit it to the sink node via relay nodes timely. Relay nodes must dissipate some energy to perform this task. So, the relay nodes and cluster heads face the challenge of energy balancing. Hence, choosing the optimal cluster heads and relay nodes is necessary to balance the energy among the sensor nodes. In this context, this paper presents a novel clustering algorithm to balance energy by considering different metrics of WSNs, including distance, energy, link lifetime, and delay characteristics—using a relay node, etc.In this paper, a Hybrid Heuristic Data Aggregation (HHDAP) Protocol is used by combining particle swarm optimization (PSO) and improved Ant colony optimization (ACO).Through this HHDAP algorithm, the relay nodes are chosen based on a sensor node's distance, energy, link lifetime, and delay metrics. This work is simulated using NS2, and the performance of proposed and existing works are evaluated. The results show the performance improvements of the proposed work over the existing algorithms in terms of different quality of service metrics.

We analyze the effects of the nonlinear distortions, introduced by the transmitting high-power amplifier (HPA), on the performance of the linear decorrelating multiuser detector in direct-sequence code-division multiple-access (DS-CDMA) downlink systems. By assuming and motivating the Gaussian distribution of the nonlinear distortion noise, the symbol-error rate (SER) and the total degradation (TD) has been derived theoretically in additive white Gaussian noise (AWGN) and frequency-flat Rayleigh fading channels. Simulation results show that the analytical model is quite accurate in many scenarios.