LAR-CC: Large atomic regions with conditional commits

Transactional memory (TM) has been shown to be a promising programming model for multi-core systems. We developed a Software-based Transactional Memory (STM) compiler that generates efficient transactional code for transactions to run on a STM runtime without the need of transactional hardware support. Since real-world applications often invoke third party libraries available only in binary form, it is imperative for our STM compiler to support legacy binary functions and provide an efficient solution to convert those invoked inside transactions to the corresponding transactional code. Our STM compiler employs a Lightweight Dynamic Binary Translation and Optimization Module (LDBTOM) to automatically convert legacy binary functions to transactional code. In this paper, we describe our LDBTOM system, which 1) seamlessly integrates the translated code with the STM compiler generated code to run on the STM runtime, and 2) optimizes the translated code taking advantage of dynamic optimization opportunities and STM runtime information. Although the binary code is inherently harder to optimize than high-level source code, our experiment shows that it can be translated and optimized into efficient transactional code by LDBTOM.

Dynamic binary translation (DBT) is a core technologyto many important applications such as system virtualization, dynamic binary instrumentation, and security. However, there are several factors that often impede its performance: 1) emulation overhead before translation; 2) translation and optimization overhead; and 3) translated code quality. The issues also include its retargetabilitythat supports guest applications from different instruction-set architectures (ISAs) to host machines also with different ISAs-an important feature to system virtualization. In this work, we take advantage of the ubiquitous multicore platforms, and use a multithreaded approach to implement DBT. By running the translator and the dynamic binary optimizer on different cores with different threads, it could off-load the overhead incurred by DBT on the target applications; thus, afford DBT of more sophisticated optimization techniques as well as its retargetability. Using QEMU (a popular retargetable DBT for system virtualization) and Low-Level Virtual Machine (LLVM) as our building blocks, we demonstrated in a multithreaded DBT prototype, called Hybrid-QEMU (HQEMU), that it could improve QEMU performance by a factor of 2.6x and 4.1x on the SPEC CPU2006 integer and floating point benchmarks, respectively, for dynamic translation of x86 code to run on x86-64 platforms. For ARM codes to x86-64 platforms, HQEMU can gain a factor of 2.5x speedup over QEMU for the SPEC CPU2006 integer benchmarks. We also address the performance scalability issue of multithreaded applications across ISAs. We identify two major impediments to performance scalability in QEMU: 1) coarse-grained locks used to protect shared data structures, and 2) inefficient emulation of atomic instructions across ISAs. We proposed two techniques to mitigate those problems: 1) using indirect branch translation caching (IBTC) to avoid frequent accesses to locks, and 2) using lightweight memory transactions to emulate atomic instructions across ISAs. Our experimental results show that for multithread applications, HQEMU achieves 25X speedups over QEMU for the PARSEC benchmarks.

Recently, reconfigurable architectures, which outperform DSP processors, have become important. Although many compilers have been developed on a source-level, there are several practical benefits to translating the binary targeted to popular processors onto reconfigurable architectures. However, the translated code could be less optimized. In particular, it is difficult to optimize memory accesses on a binary to exploit pipeline parallelism. This paper introduces dynamic binary translation and memory access optimization to overcome the limitations of static binary translation for reconfigurable architecture. The experimental results show a promising speedup up to 3.02 compared with the code whose memory accesses is not optimized in the pipeline fashion.

Transmeta's Efficeon microprocessor is a full, system-level implementation of the x86 architecture, comprising a native VLIW microprocessor with a software layer, the Code Morphing Software (CMS), that combines an interpreter, dynamic binary translator, optimizer, and run-time system. This software layer provides unique opportunities for studying the tradeoffs between interpretation and dynamic translation with various levels of optimization, while running arbitrary PC workloads. This talk presents some results from such a study, and provides insight into what mix of these emulation modes is most desirable over the range of tested workloads.

This work aims to discover the relevant factors to predict the health condition of COVID-19 patients by employing a fresh and enhanced binary multi-objective hybrid filter-wrapper chimp optimization (EBMOChOA-FW) based feature selection (FS) approach. FS is a preprocessing approach that has been highly fruitful in medical applications, as it not only reduces dimensionality but also allows us to understand the origins of an illness. Wrappers are computationally expensive but have excellent classification performance, whereas filters are recognized as quick techniques, although they are less accurate. This study presents an advanced binary multi-objective chimp optimization method based on the hybridization of filter and wrapper for the FS task using two archives. In exceptional instances, the initial ChOA version becomes stuck at the local optima. As a result, a novel ChOA termed EBMOChOA is developed here by integrating the Harris Hawk Optimization (HHO) into the original ChOA to improve the optimizer’s search capabilities and broaden the usage sectors. The location change step in the ChOA optimizer is separated into three parts: modifying the population using HHO to produce an HHO-based population; creating hybrid entities according to HHO-based and ChOA-based individuals; and altering the search agent in the light of greedy technique and ChOA’s tools. The effectiveness of the EBMOChOA-FW is proven by comparing it to five other well-known algorithms on nine different benchmark datasets. Then its strengths are applied to three real-world COVID-19 datasets to predict the health condition of COVID-19 patients.

Indirect branches have historically been a challenge for microarchitectures and code generators alike. The recent steady increase in indirect branch predictability has translated into continual performance improvements especially for Out-of-Order processors which benefit more readily from improvements in branch prediction. In contrast, in-order processors which rely on code generators for performance are still challenged by indirect branches; they are a frequent source of issue stalls and the large number of indirect branch targets and unbiased nature of indirect branches complicate the use of traditional branch handling techniques like assert conversion and predication.

Both dynamic binary translation systems and optimization systems store the translated or optimized code in the software maintained code cache for reuse. The performance of the code cache is crucial. Translated code is usually organized as code blocks in the code cache and each code block transfer control to the next one through a control transfer instruction. As the target address of a control transfer instruction is in the form of its source program counter, the conventional code cache system has to check the address mapping table for the translated target address to find the required target code block, which will cause considerable performance degradation. Control transfer instructions can be divided into two categories as direct control transfer instructions and indirect control transfer instructions. For indirect control transfer instructions, the target address is hold in the register or memory element whose content can be changed during the execution of the program. It is difficult to chain the indirect control transfer instructions with a fixed translated target address through pure software approaches. A novel indirect control transfer chaining approach is proposed in this paper. The principle of the technique is to insert custom chaining instructions into the translated code block while translating the indirect control transfer instructions and execute those chaining instructions to implement dynamical chaining. Some special hardware and software assists are proposed in this paper. Evaluation of the proposed approach is conducted on a code cache simulator. Experiment results show that our hardware assisted indirect control transfer instruction chaining approach can improve the performance of the code cache system dramatically.Keywordscode cacheindirect control transfer instructiondynamic chainingsimulator

Most dynamic binary translators (DBT) and optimizers (DBO) target binary traces, i.e. frequently executed paths, as code regions to be translated and optimized. Code region formation is the most important first step in all DBTs and DBOs. The quality of the dynamically formed code regions determines the extent and the types of optimization opportunities that can be exposed to DBTs and DBOs, and thus, determines the ultimate quality of the final optimized code. The Next-Executing-Tail (NET) trace formation method used in HP Dynamo is an early example of such techniques. Many existing trace formation schemes are variants of NET. They work very well for most binary traces, but they also suffer a major problem: the formed traces may contain a large number of early exits that could be branched out during the execution. If this happens frequently, the program execution will spend more time in the slow binary interpreter or in the unoptimized code regions than in the optimized traces in code cache. The benefit of the trace optimization is thus lost. Traces/regions with frequently taken early-exits are called delinquent traces/regions. Our empirical study shows that at least 8 of the 12 SPEC CPU2006 integer benchmarks have delinquent traces. In this paper, we propose a light-weight region formation technique called Early-Exit Guided Region Formation (EEG) to improve the quality of the formed traces/regions. It iteratively identifies and merges delinquent regions into larger code regions. We have implemented our EEG algorithm in two LLVM-based multi-threaded DBTs targeting ARM and IA32 instruction set architecture (ISA), respectively. Using SPEC CPU2006 benchmark suite with reference inputs, our results show that compared to an NET-variant currently used in QEMU, a state-of-the-art retargetable DBT, EEG can achieve a significant performance improvement of up to 72% (27% on average), and to 49% (23% on average) for IA32 and ARM, respectively.

Most dynamic binary translators (DBT) and optimizers (DBO) target binary traces, i.e. frequently executed paths, as code regions to be translated and optimized. Code region formation is the most important first step in all DBTs and DBOs. The quality of the dynamically formed code regions determines the extent and the types of optimization opportunities that can be exposed to DBTs and DBOs, and thus, determines the ultimate quality of the final optimized code. The Next-Executing-Tail (NET) trace formation method used in HP Dynamo is an early example of such techniques. Many existing trace formation schemes are variants of NET. They work very well for most binary traces, but they also suffer a major problem: the formed traces may contain a large number of early exits that could be branched out during the execution. If this happens frequently, the program execution will spend more time in the slow binary interpreter or in the unoptimized code regions than in the optimized traces in code cache. The benefit of the trace optimization is thus lost. Traces/regions with frequently taken early-exits are called delinquent traces/regions. Our empirical study shows that at least 8 of the 12 SPEC CPU2006 integer benchmarks have delinquent traces.

A novel quantum grasshopper optimization algorithm for feature selection

The security of hardware-software systems is at risk from a wide range of attack vectors that appear at various stages during the execution of machine code. The existing approaches for repairing software defects have numerous restrictions with respect to their applicability and functionality and to the range of vulnerabilities that can be identified and eliminated.We propose an approach for removing software errors in program code that is based on just-in-time compilation in a virtual execution environment. The virtual environment uses static, dynamic, and hybrid analyses of the intermediate representation of vulnerable code and re-compiles such code to be safe.The language of code annotations allows us to manage static and dynamic analyses and code transformations. We can change the level of analysis and the amount of time spent on such analyses by dynamically adapting the precision.

This paper presents three ideas that focus on improving the execution of high-level parallel code in GPUs. The first addresses programs that include multiple parallel blocks within a single region of GPU code. A proposed compiler transformation can split such regions into multiple, leading to the launching of multiple kernels, one for each parallel region. Advantages include the opportunity to tailor grid geometry of each kernel to the parallel region that it executes and the elimination of the overheads imposed by a code-generation scheme meant to handle multiple nested parallel regions. Second, is a code transformation that sets up a pipeline of kernel execution and asynchronous data transfer. This transformation enables the overlap of communication and computation. Intricate technical details that are required for this transformation are described. The third idea is that the selection of a grid geometry for the execution of a parallel region must balance the GPU occupancy with the potential saturation of the memory throughput in the GPU. Adding this additional parameter to the geometry selection heuristic can often yield better performance at lower occupancy levels.

User interface prototypes are effective structure for describing as models for web application development thanks to their graphical and dynamic architecture. It provides the benefits such as language independent development, less error-prone and increased quality. The executable programming codes are created by code transformation feature of model-driven development tools as well. Nevertheless, this technique brings the problems along all its benefits. First of all, code transformation from user interfaces by development tools, creates complicated structure to analyze and modify. Another challenge is to deal with the processes which are triggering each other. In addition, data connected process adaptation is a problem as well. All these issues eventually require the integration of discrete modules. This study provides not only a proposal structure to deal with integration problem in web development, but also provides the evaluation criteria for classification of the integration processes.

Dynamic multi-objective optimization problems (DMOPs) have become a research hotspot in engineering optimization, because their objective functions, constraints, or parameters may change over time, while quickly and accurately tracking the changing Pareto optimal set (POS) during the optimization process. Therefore, solving dynamic multi-objective optimization problems presents great challenges. In recent years, transfer learning has been proved to be one of the effective means to solve dynamic multi-objective optimization problems. However, this paper proposes a new transfer learning method based on clustering difference to solve DMOPs (TCD-DMOEA). Different from the existing methods, it uses the clustering difference strategy to optimize the population quality and reduce the data difference between the target domain and the source domain. On this basis, transfer learning technology is used to accelerate the construction of initialization population. The advantage of the TCD-DMOEA method is that it reduces the possibility of negative transfer and improves the performance of the algorithm by improving the similarity between the source domain and the target domain. Experimental results show that compared with several advanced dynamic multi-objective optimization algorithms based on different benchmark problems, the proposed TCD-DMOEA method can significantly improve the quality of the solution and the convergence speed.

Summary This paper describes an investigation of methods for fatigue strength improvement of welded joints, such a TIG dressing, hammer peening and burr grinding. The main results may be summarised as follows. 1 A fatigue strength improvement is achieved by all treatment methods considered in the present research study. Most notably, the effect of burr grinding is not very dependent on the effective stress range and produces a strong fatigue strength improvement effect. 2 The fatigue strength improvement effect produced by TIG dressing is only found in the short crack region, and its fatigue strength improvement effect can be evaluated through consideration of the stress concentration reducing effect due to weld toe shape improvement. 3 The fatigue strength improvement effect produced by hammer peening strongly depends on the stress range. Little such effect is found in the Nc fatigue crack initiation region adopted in the present research study. In the Np fatigue crack propagation region, however, a strong effect is evident. This is attributable to a stress concentration reducing effect due to weld toe shape improvement and a fatigue strength improvement due to the effect of the compressive residual stress introduced down to some specific depth (around 4 mm according to the measurement results obtained in the present research study) under this treatment. The ditch introduced by hammer peening treatment acts as a crack initiation source. To ensure that the effect due to hammer peening is more fully exhibited, it is necessary to apply burr grinding treatment to the weld toe before hammer peening as well as to prevent ditch formation by use of a hammer with a smaller tip radius. 4 The fatigue strength improvement effect produced by burr grinding is only found in the short crack Nc region. It depends for its effect on a stress concentration reducing effect due to weld toe improvement, although the effect thus produced is strong. To ensure that the stress concentration reducing effect is more fully exhibited, it is desirable to minimise base metal denting. This treatment also offers scope for some reduction in residual stress through its ability to machine off a large region using a burr grinder tip with an extremely large radius of curvature, and this aspect warrants further investigation in future.