Large Dynamic Range Accurate Digitally Programmable Delay Line with 250-ps Resolution

This paper presents the design and implementation of a new digital-to-time converter (DTC). The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.17~+0.13 LSB and −0.35~+0.62 LSB, respectively. This DTC builds coarse and fine Vernier delay lines constructed by programmable delay lines (PDLs) to ensure high performance delay. Benefited by the close-loop feedback mechanism of the PDLs’ control module, the presented DTC has excellent voltage and temperature stability. What is more, the proposed DTC can be implemented in a single field programmable gate array (FPGA) chip.

Regular Expressions (RegExes) are widely used in various applications to identify strings of text. Their flexibility, however, increases the complexity of the detection system and often limits the detection speed as well as the total number of RegExes that can be detected using limited resources. The two classical detection methods, Deterministic Finite Automaton (DFA) and Non-Deterministic Finite Automaton (NFA), have the potential problems of prohibitively large memory requirements and a large number of concurrent operations, respectively. Although recent schemes addressing these problems to improve DFA and NFA are promising, they are inherently limited by their scalability, since they follow the state transition model in DFA and NFA, where the state transitions occur per each character of the input. We recently proposed a scalable RegEx detection system called Lookahead Finite Automata (LaFA) to solve these problems with three novel ideas: 1. Provide specialized and optimized detection modules to increase resource utilizations. 2. Systematically reordering the RegEx detection sequence to reduce number of concurrent operations. 3. Sharing states among automata for different RegExes to reduce resource requirements. In this paper, we propose an efficient hardware architecture and prototype design implementation based on LaFA. Our proof-of-concept prototype design is built on a fraction of a single commodity Field Programmable Gate Array (FPGA) chip and can accommodate up to twenty-five thousand (25k) RegExes. Using only 7% of the logic area and 25% of the memory on a Xilinx Virtex-4 FX100, the prototype design can achieve 2-Gbps (gigabits-per-second) detection throughput with only one detection engine. We estimate that 34-Gbps detection throughput can be achieved if the entire resources of a state-of-the-art FPGA chip are used to implement multiple detection engines.

Face detection has been widely used in many fields such as security, intelligent human interface etc., and concerns on how to meet the criterion of miniature and real-time have gradually become independent research topics. Traditionally, systems of face detection/recognition are either implemented in very specific hardware or software system. This paper tailors an algorithm of face detection using skin color and presents an efficient implementation on a single Field Programmable Gate Array (FPGA) chip. The implementation exploits the inherit parallelism of hardware and takes advantages of hardware multiply-accumulate units and shift register(RAM-Based) units on FPGA. The entire system uses a single FPGA coupled to a pair of SDRAM chips, and no extra parts. The system was implemented and tested with face detection on a 1280×1024 frame taking 16.66 ms (60 frames per second ). This system can be used as a reference for lightweight embedded vision systems.

The continuous development of more accurate and selective bio- and chemo-sensors has led to a growing use of sensor arrays in different fields, such as health monitoring, cell culture analysis, bio-signals processing, or food quality tracking. The analysis and information extraction from the amount of data provided by these sensor arrays is possible based on Machine Learning techniques applied to sensor fusion. However, most of these computing solutions are implemented on costly and bulky computers, limiting its use in in-situ scenarios outside complex laboratory facilities. This work presents the application of machine learning techniques in food quality assessment using a single Field Programmable Gate Array (FPGA) chip. The characteristics of low-cost, low power consumption as well as low-size allow the application of the proposed solution even in space constrained places, as in food manufacturing chains. As an example, the proposed system is tested on an e-nose developed for beef classification and microbial population prediction.

In a radar application, Time Signal Generator (TSG) is used to generate timing and control signals which helps radar to operate in different functions. The functions include tracking, detection, and hold mode. Timing Signal Generator is the heart of radar applications. Timing Signal Generator is the main part of radar application, which is responsible for synchronization between Transmitter and receiver for the transmitted signal. In this work, an implementation of timing signal using a Hardware Description Language (HDL) language-based state machine which is responsible for enabling Direct Digital Synthesis and Analog to Digital Converter in the Transmitter and receiver window. Timing Signal Generator implementation on Field Programmable Gate Array is preferred as the entire Timing signal generator unit can be assembled on a single Field programmable gate array chip, and conditional modification can be performed remotely, which is cost-effective. Timing signal generator generation begins by providing an arbitrary frequency and phase signal configuration to DDS-AD9854 from Field programmable gate array. Direct digital synthesis block generates a single-tone signal and Binary Phase Shift Keying signal and a chirp signal based on an input arbitrary signal sent by ZYBO-7010 FPGA.

Deep Packet Inspection (DPI) technology has been widely deployed in Network Intrusion Detection System (NIDS) to detect attacks and viruses. State-of-the-art NIDS uses Deterministic Finite Automata (DFA) to perform regular expression matching for its stable matching speed. However, traditional DFA algorithm’s throughput is limited by the input character’s width (usually one character per time). In this paper, we present an architecture named Parallel-DFA to accelerate regular expression matching by scanning multiple characters per time. Experimental results show that, our architecture can achieve as high as 1200 Gbps (1.17 Tbps) rate on current single Field-Programmable Gate Array (FPGA) chip. This makes it a very practical solution for NIDS in 100G Ethernet standard network, which is currently the fastest approved standard of Ethernet. To the best of our knowledge, this is the fastest matching performance architecture on a single FPGA chip. Besides, the throughput is nearly 3 orders of magnitude (916\(\times \)) than that of original DFA implemented on software. Our architecture is about 183.2\(\times \) efficiency than that of original DFA.

The goal of this paper is to implement the secretion mechanism of the Thyroid Hormone (TH) based on bio-mathematical differential eqs. (DE) on an FPGA chip. Hardware Descriptive Language (HDL) is used to develop a behavioral model of the mechanism derived from the DE. The Thyroid Hormone secretion mechanism is simulated with the interaction of the related stimulating and inhibiting hormones. Synthesis of the simulation is done with the aid of CAD tools and downloaded on a Field Programmable Gate Arrays (FPGAs) Chip. The chip output shows identical behavior to that of the designed algorithm through simulation. It is concluded that the chip mimics the Thyroid Hormone secretion mechanism. The chip, operating in real-time, is computer-independent stand-alone system.

A high-resolution, multi-stop, time-to-digital converter for nuclear time-of-flight measurements

In this paper, we introduce a new development system for creating real-time image processing hardware using custom computing machines with multiple Field Programmable Gate Array (FPGA) chips. Three distinct processes are accomplished within the development system: design entry, verification, and translation. A library of modules that implement common low-level machine vision functions is used to create complex designs based on a dataflow graph representation. The library's low-level image processing modules contain both gate-level and chip-level hardware components, of which the gate-level components are compiled into the functionality of available FPGA chips. Standard interfaces are established for input/output of the modules, allowing for the creation of sophisticated software support tools. Experimental results verify the utility of this development system for easily creating real-time machine vision hardware using multiple FPGA-based custom computing machines.

Raman spectrometer has been widely used as an identification tool for analyzing material structure and composition in many fields. However, Raman scattering echo signal is very weak, about dozens of photons at most in one laser plus signal. Therefore, it is a great challenge to design a Raman spectrum data acquisition system which could accurately receive the weak echo signal. The system designed in this paper receives optical signals with the principle of photon counter and could detect single photon. The whole system consists of a photoelectric conversion module H7421-40 and a photo counting card including a field programmable gate array (FPGA) chip and a PCI9054 chip. The module H7421-40 including a PMT, an amplifier and a discriminator has high sensitivity on wavelength from 300nm to 720nm. The Center Wavelength is 580nm which is close to the excitation wavelength (532nm), QE 40% at peak wavelength, Count Sensitivity is 7.8*10⁵(S^-1PW^-1) and Count Linearity is 1.5MHZ. In FPGA chip, the functions are divided into three parts: parameter setting module, controlling module, data collection and storage module. All the commands, parameters and data are transmitted between FPGA and computer by PCI9054 chip through the PCI interface. The result of experiment shows that the Raman spectrum data acquisition system is reasonable and efficient. There are three primary advantages of the data acquisition system: the first one is the high sensitivity with single photon detection capability; the second one is the high integrated level which means all the operation could be done by the photo counting card; and the last one is the high expansion ability because of the smart reconfigurability of FPGA chip.

A single chip FPGA-based solution for controlling of multi-unit PMSM motor with time-division multiplexing scheme

This paper presents a methodology for simulating and automatically optimizing distributed cyber-physical systems using reconfigurable hardware. By mapping an entire system of distributed devices including the buses onto a single Field Programmable Gate Array (FPGA), it becomes possible to make changes to the architecture, including the topology, using reconfiguration. This approach enables accurate rapid prototyping of distributed architectures, while also closing the gap between early simulation results and the final design, leading to a more robust optimization. Furthermore, the system can be simulated and optimized within a Hardware-in-the-Loop (HIL) setup due to its cycle- and bit-accurate execution in real-time. We introduce the general concept and building blocks that enable a faster and more accurate simulation and optimization: (1) The details of our approach for mapping devices, network interfaces, and buses onto an FPGA are presented. (2) An optimization model is proposed that encodes the topology, task distribution, and communication in a very efficient representation. Finally, the implementation and integration of the methodology is presented and discussed.

Today, cryptographic security depends primarily on having strong keys and keeping them secret. The keys should be produced by a reliable and robust to external manipulations generators of random numbers. To hamper different attacks, the generators should be implemented in the same chip as a cryptographic system using random numbers. It forces a designer to create a random number generator purely digitally. Unfortunately, the obtained sequences are biased and do not pass many statistical tests. Therefore an output of the random number generator has to be subjected to a transformation called post-processing. In this paper the hash function SHA-256 as post-processing of bits produced by a combined random bit generator using jitter observed in ring oscillators (ROs) is proposed. All components – the random number generator and the SHA-256, are implemented in a single Field Programmable Gate Array (FPGA). We expect that the proposed solution, implemented in the same FPGA together with a cryptographic system, is more attack-resistant owing to many sources of randomness with significantly different nominal frequencies.

In order to reduce the resources utilization of Field Programmable Gate Array (FPGA) chip thereby using one FPGA to control multiple motors together, a novel time-division multiplexing (TDM) method is proposed in this paper. The field-oriented control (FOC) algorithm is developed using Xilinx system generator (XSG) in Matlab/Simulink environment. Due to the fast calculation speed of FPGA and the pipeline optimization technology, the execution time of FOC algorithm can reach 100 kHz. In order to verify the proposed TDM method, the dual-motor scenario is studied in this paper. Experimental results show that by adopting the proposed TDM method, the resource utilization of the FPGA chip can be further greatly reduced.

The MIL-STD-188-220 protocol is the interconnection standard between DMTDs in battlefield of America DOD. It's the only standardized protocol in tactical mobile networks by now. The protocol models and performance simulations are widely discussed, but mostly based on software simulations and rarely in the implementation issues. This paper is mainly focused on the protocol implementations and system performance analysis. The implementation is a MIL-STD-220C compatible device, which completing the entire data link layer operation and a part of network layer operation in a single FPGA(field programmable gate array) chip to achieve minimum response time and stable performance. The communication adapter function diagram, working flowchart and performance figures are listed.