Late Breaking Results: Scalable GPU-Friendly Parallelization for Sweep-Based Maze Routing

In this paper, we present a new global router, NTHU-Route, for modern designs. NTHU-Route is based on iterative rip-ups and reroutes, and several techniques are proposed to enhance our global router. These techniques include (1) a history based cost function which helps to distribute overflow during iterative rip-ups and reroutes, (2) an adaptive multi-source multi-sink maze routing method to improve the wirelength of maze routing, (3) a congested region identification method to specify the order for nets to be ripped up and rerouted, and (4) a refinement process to further reduce overflow when iterative history based rip-ups and reroutes reach bottleneck. Compared with two state-of-the-art works on ISPD98 benchmarks, NTHU-Route outperforms them in both overflow and wirelength. For the much larger designs from the ISPD07 benchmark suite, our solution quality is better than or comparable to the best results reported in the ISPD07 routing contest.

In this paper, we study the well-posedness and stability of a wave equation with infinitely structural memory, herein the memory kernel function does not satisfy the monotonicity. For the model, the history function space setting is a main difficulty because the usual space setting will lead the shift semigroup to be a unbounded semigroup. In the present paper, we modify the history function space setting and prove the well-posedness of the system. Further we study the stability of the system via Lyapunov function method. By constructing appropriate Lyapunov function, we show that the energy function of the system decays exponentially if the memory kernel function satisfies some conditions. Finally, we give an example of the memory kernel function that is not monotone but satisfies all conditions proposed in the present paper.

A gate array router that utilizes horizontal and vertical over-cell routing channels to increase cell density is described. Logic macros, with fixed intraconnect metal that may span several cell columns, are mapped onto the array producing partially filled routing channels. Macro interconnects are loosely assigned to the partially filled horizontal and vertical routing channels during global routing. Each loose horizontal channel segment is assigned to a channel track using a maze router. Vertical channel segments are completed by a modified dogleg channel router.

The advancement of the Internet of Things has enabled numerous applications ranging from smart wearable to connected vehicles. However, the limited energy and memory resources of low-end IoT devices significantly impede their further flourish. In this article, we consider a system that consists of an IoT device and an edge server. The edge server stores code blocks for the IoT device and loads required blocks to the IoT device for execution thereby alleviates the latter from the limited memory resource. Furthermore, the IoT device can harvest energy from the ambient energy sources to achieve a sustainable operation. To deal with the dynamic energy harvesting process and block request process, we propose a stochastic block prefetching framework (BPF) to optimize the user experienced delay. The BPF assists the IoT device to intelligently prefetch blocks from the edge server according to the historical user behaviors. The BPF consists of three modules, i.e., estimation module, prefetching module, and dual learning module. The estimation module measures the probability of block being requested in the future. The prefetching module requests blocks from the edge server according to the available energy and memory. The dual learning module helps to accelerate the convergence of the framework. The numerous simulation results are provided to verify the effectiveness of the proposed framework.

We consider an inverse problem for a parabolic equation with memory effect. This inverse problem aims to identify the memory kernel function from a fixed point measurement data. Based on the fixed point arguments, we derive the global in time existence and uniqueness of our inverse problem. Moreover, we present a numerical algorithm to reconstruct the memory kernel function. Numerical simulations show the effectiveness of the proposed method.

In VLSI design flow, the designer has better control over critical parameters such as power consumption and delay at higher levels of abstraction. Trade-offs and design changes are easier to accomplish at architectural and system levels. The decisions taken at these levels have a large impact on the final quality of the design. Power consumption has become a vital issue in all modern designs. However, actual information on this important metric is available only after the back-end phase when the design is committed to silicon. At this juncture, very little can be done to optimize power. Therefore, power estimation at higher levels is an extremely crucial step in executing power aware designs. Power estimation techniques can be applied at all abstraction levels in the low power design flow, of which highest level is system level. The design process at higher abstraction level shields the designer's crucial time and effort in power estimation. It is challenging to extract and analyse knowledge about the circuit of the system at the system level. If we estimate the power at this level, large power savings can be done and also power optimized design changes can be done. This paper describes an augmented power estimation methodology for intellectual property (IP) components. The method uses statistical methods to isolate a set of input influencing the output power for a particular mode of operation. The power model is developed as a function of parameters such as signal probability, transition density and spatial correlation. The proposed method was evaluated on a SDRAM controller core. The power estimation error varies from 0.3% to 12.5%.

Wire routing, an important step in modern VLSI design, is increasingly responsible for timing closure and manufacturability. The CAD community has witnessed remarkable improvements in speed and quality of global routing algorithms in response to the inaugural ISPD 2007 Global Routing Contest, where prizes were awarded for best results on a new set of large industry benchmarks.

Routability is a critical issue in VLSI design flow. To address this issue, the routability-driven placement contests [1, 2] held at ISPD11 and DAC12 promote the development of routability-driven placers such as those in [4-6]. ISPD11 and DAC12 contests adopt metrics that are based on global routing solutions to evaluate the routability of placement solutions. However, such global-routing-based metrics typically ignore local congestion, and they cannot evaluate the actual routability effectively. In this work, we develop a translator that allows us to feed the placement solutions of mPL [3], NTUplace [4], Ripple [5], and SimPLR [6] into a commercial router for detailed routing. We then analyze the detailed routing result of each placement solution to better understand the issues that may cause routing violations. Moreover, we examine the suitability of using the ISPD11 and DAC12 metrics in predicting routability. Our findings indicated that the metrics might not reliably predict actual routability, in terms of the number of (detailed) routing violations.

The increasing complexity of interconnection designs has enhanced the importance of research into global routing when seeking high-routability (low overflow) results or rapid search paths that report wirelength estimations to a placer. This work presents two routing techniques, namely circular fixed-ordering monotonic routing and evolution-based rip-up and rerouting using a two-stage cost function in a high-performance congestion-driven 2-D global router. We also propose two efficient via-minimization methods, namely congestion relaxation by layer shifting and rip-up and reassignment, for a dynamic programming-based layer assignment. Experimental results demonstrate that our router achieves performance similar to the first two winning routers in ISPD 2008 Routing Contest in terms of both routability and wirelength at a 1.05 × and 18.47 × faster routing speed. Moreover, the proposed layer assignment achieves fewer vias and shorter wirelength than congestion-constrained layer assignment (COLA).

Classification is a quite relevant task within data analysis field. This task is not a trivial task and different difficulties can arise depending on the nature of the problem. All these difficulties can become worse when the datasets are too large or when new information can arrive at any time. Incremental learning is an approach that can be used to deal with the classification task in these cases. It must alleviate, or solve, the problem of limited time and memory resources. One emergent approach uses concentration bounds to ensure that decisions are made when enough information supports them. IADEM is one of the most recent algorithms that use this approach. The aim of this paper is to improve the performance of this algorithm in different ways: simplifying the complexity of the induced models, adding the ability to deal with continuous data, improving the detection of noise, selecting new criteria for evolutionating the model, including the use of more powerful prediction techniques, etc. Besides these new properties, the new system, IADEM-2, preserves the ability to obtain a performance similar to standard learning algorithms independently of the datasets size and it can incorporate new information as the basic algorithm does: using short time per example.

Effective Big Data analytics pose several difficult challenges for modern data management architectures. One key such challenge arises from the naturally streaming nature of big data, which mandates efficient algorithms for querying and analyzing massive, continuous data streams (that is, data that is seen only once and in a fixed order) with limited memory and CPU-time resources. Such streams arise naturally in emerging large-scale event monitoring applications; for instance, network-operations monitoring in large ISPs, where usage information from numerous sites needs to be continuously collected and analyzed for interesting trends. In addition to memory- and time-efficiency concerns, the inherently distributed nature of such applications also raises important communication-efficiency issues, making it critical to carefully optimize the use of the underlying network infrastructure. In this talk, we introduce the distributed data streaming model, and discuss recent work on tracking complex queries over massive distributed streams, as well as new research directions in this space.KeywordsData StreamRemote SiteLarge Data BaseStreaming DataLocal QueryThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

In this paper, we propose a new global router, BoxRouter, powered by the concept of box expansion, progressive integer linear programming (PILP), and adaptive maze routing (AMR). BoxRouter first uses a simple prerouting strategy to predict and capture the most congested region with high fidelity as compared to the final routing. Based on progressive box expansion initiated from the most congested region, BoxRouting is performed with PILP and AMR. Our PILP is shown to be much more efficient than the traditional ILP in terms of speed and quality, and the AMR based on multisource multitarget with bridge model is effective in minimizing the congestion and wirelength. It is followed by an effective postrouting step, which reroutes without rip-up to enhance the routing solution further and obtain smooth tradeoff between wirelength and routability. Our experimental results show that the BoxRouter significantly outperforms the state-of-the-art published global routers, e.g., 91 % better routability than Labyrinth (with 14% less wirelength and 3.3times speedup), 79% better routability than Chi-dispersion router (with similar wirelength and 2times speedup), and 4.2% less wirelength and 16times speedup than a multicommodity flow-based router (with similar routability). Additional enhancement in box expansion and postrouting further improves the result with similar wirelength but much better routability than the latest work in global routing.

Global routing faces an increasing problem size and urgent demand on improvement in solution quality. Despite of the recent developments of global routers, there exist only two types of choices: slow 3D routers with good solution quality or efficient 2D routers with relatively poor solution quality. We propose a multi-level 3D global router called MGR to fill the gap. MGR resorts to an efficient multi-level framework to reroute nets in the congested region on the 3D grid graph. Routing on the coarsened grid graph speeds up the global router while 3D routing introduces less vias. The powerful multi-level rerouting framework wraps three innovative routing techniques together: adaptive resource reservation in coarsening process, a new 3-terminal maze routing algorithm and network flow based solution propagation in uncoarsening process. As a result, MGR can achieve the solution quality close to 3D routers with comparable runtime of 2D routers.

Global routing for modern large-scale circuit designs has attracted much attention in the recent literature. Most of the state-of-the-art academic global routers just work on a simplified routing congestion model that ignores the essential via capacity for routing through multiple metal layers. Such a simplified model would easily cause fatal routability problems in subsequent detailed routing. To remedy this deficiency, we present in this paper a more effective congestion metric that considers both the in-tile nets and the residual via capacity for global routing. With this congestion metric, we develop a new global router that features two novel routing algorithms for congestion optimization, namely least-flexibility-first routing and multi-source multi-sink escaping-point routing. The least-flexibility-first routing processes the nets with the least flexibility first, facilitating a quick prediction of congestion hot spots for the subsequent nets. Enjoying lower time complexity than traditional maze and A*-search routing, in particular, the linear-time escaping-point routing guarantees to find the optimal solution and achieves the theoretical lower-bound time complexity. Experimental results show that our global router can achieve very high-quality routing solutions with more reasonable via usage, which can benefit and correctly guide subsequent detailed routing.

Modern logic and physical synthesis tools provide numerous options and parameters that can drastically affect design quality; however, the large number of options leads to a complex design space difficult for human designers to navigate. Fortunately, machine learning approaches and cloud computing environments are well suited for tackling complex parameter tuning problems like those seen in VLSI design flows. This paper proposes a holistic approach where online and offline machine learning approaches work together for tuning industrial design flows. We describe a system called SynTunSys (STS) that has been used to optimize multiple industrial high-performance processors. STS consists of an online system that optimizes designs and generates data for a recommender system that performs offline training and recommendation. Experimental results show the collaboration between STS online and offline machine learning systems as well as insight from human designers provide best-of-breed results. Finally, we discuss potential new directions for research on design flow tuning.