LDPC decoding for CMMB utilizing OpenMP and CUDA parallelization

In this paper, a multi-rate Low Density Parity Check (LDPC) decoder for China Mobile Multimedia Broadcasting (CMMB) is proposed. The architecture of proposed decoder only utilizes a parallel with 2 for  rate and 1 for ¾ rate can meet the throughput requirements for the CMMB standard. Various techniques are employed to significantly reduce memory and logic resources, including a special quantization scheme, solution for memory collision, the reuse properties of layered decoding, compressing of check-to-variable messages and the layered algorithm, which lead to a reduction of memory and logic resources by a half.

Low-Density Parity-Check (LDPC) codes are powerful error correcting codes. LDPC decoders have been implemented as efficient error correction codes on dedicated VLSI hardware architectures in recent years. This paper describes two strategies to parallelize min-sum decoding of irregular LDPC codes. The first implements min-sum LDPC decoders on multicore platforms using OpenMP, while the other uses the Compute Unified Device Architecture (CUDA) to parallelize LDPC decoding on Graphics Processing Units (GPUs). Empirical studies on data with various scales show that the performance of these decoding processes is improved by these parallel strategies and the GPUs provide more efficient, fast implementation decoder.

Based on the principle of QR loop iterations, this paper implements a parallel algorithm based on the hardware of GPU (Graphic Process Unit) by using routines from CUDA (Computer Unified Device Architecture) to find the eigenvalues of general matrices. CPU and GPU computing card form a client-server computing framework. Here, CPU can be regarded as a client and GPU card is considered as a computing server. For the experiment environment, this paper chooses a GPU card with the model of NVIDIA GeForce GTX460 as a server side and a CPU with the model of Intel Core i5-760 quad-core as a client side. Win7 64-bit is selected as the operating system. The parallel implementation consists of two parts:PA H and PA QR. PA H is a procedure that transforms a matrix A into the Hessenberg matrix B. PA QR is the actual parallel algorithm of the QR iterations that is imposed on the Hessenberg matrix B for finding eigenvalues of the general matrix A. The speedup ratio of the proposed algorithm is jarless when the number of iterations becomes greater. The experimental results show that the parallel implementation with CUDA on GPU only makes use of less running time than traditional sequential algorithms. The speedup ratio of PA H is between 1.79 and 7.81. The speedup ratio of PA QR is between 3.24 and 118.9. Especially, when the order of general matrix equals 8192, the amount of iterations becomes 10000. The speedup ratio of the PA-H and the PA QR can run up to 7.81 and 118.9 respectively.

Watershed analysis, as a fundamental component of digital terrain analysis, is based on the Digital Elevation Model (DEM), which is a grid (raster) model of the Earth surface and topography. Watershed analysis consists of computationally and data intensive computing algorithms that need to be implemented by leveraging parallel and high-performance computing methods and techniques. In this paper, the Multiple Flow Direction (MFD) algorithm for watershed analysis is implemented and evaluated on multi-core Central Processing Units (CPU) and many-core Graphics Processing Units (GPU), which provides significant improvements in performance and energy usage. The implementation is based on NVIDIA CUDA (Compute Unified Device Architecture) implementation for GPU, as well as on OpenACC (Open ACCelerators), a parallel programming model, and a standard for parallel computing. Both phases of the MFD algorithm (i) iterative DEM preprocessing and (ii) iterative MFD algorithm, are parallelized and run over multi-core CPU and GPU. The evaluation of the proposed solutions is performed with respect to the execution time, energy consumption, and programming effort for algorithm parallelization for different sizes of input data. An experimental evaluation has shown not only the advantage of using OpenACC programming over CUDA programming in implementing the watershed analysis on a GPU in terms of performance, energy consumption, and programming effort, but also significant benefits in implementing it on the multi-core CPU.

This paper propose a new flexible low-density parity-check (LDPC) decoding architecture that can be dynamically reconfigured according to a parity-check matrix which changes as code rate or block length varies. Since the LDPC codes are adopted in standards such as DVB-S2, IEEE 802.1 In and IEEE 802.16e and each standard allows various code rates and block lengths, an LDPC decoder architecture that could support multiple code rates and code block lengths is needed. The proposed architecture employs Benes network to implement configurable interconnection network. In the proposed architecture the number of levels and the delay of the interconnection network is reduced by using broadcasting technique which transmits reduced messages to save the complexity of the interconnection network. The number of processing units in the proposed partially parallel architecture is determined by investigating the relation between hardware complexity and throughput. By applying pipelining to the processing units, decoding throughput is increased. To verify the proposed architecture, a flexible LDPC decoder is implemented using a 0.18 mum CMOS process. The decoder occupies an area of 16.261 mm and runs correctly at the frequency of 212 MHz resulting in 1 Gbps decoding throughput.

With increasing demand of low complexity, higher performance systems ITU adopted Wi-Fi and Wi-Max as one of the IMT 2000 Technologies. Wi-Fi and Wi-Max technologies are major global cellular wireless standards. IEEE 802.16e standards use LDPC (Low Density Parity Check) based SFN (Single Frequency Network) networks. These codes were introduced in 1962 by Gallager. LDPC codes for Wi-max and Wi-Fi is based on the set of one or more fundamental LDPC codes, each of which is systematic linear block codes. These codes can accommodate various code rates and packet sizes. LDPC with the help of high frequency powerful processors is error correcting codes which allows transmission at rates in close proximity to Shannon's limit for large block length. With this paper authors are describing various LDPC codes with low complexity and high performance used for Wi-Fi and Wi-max technologies.

Purpose: For microdosimetric calculation event-by-event Monte Carlo (MC) simulation is considered the most accurate, but it is very time-consuming. In this work we present an event-by-event MC simulation of low energy electron and proton for accelerated microdosimetric MC simulations on a graphic processing unit (GPU). Methods: The MC simulation of particle was implemented in C and executed on a multi-core CPU, and a commercially available general purpose GPU using the compute unified device architecture (CUDA). Additionally, a hybrid implementation scheme was realized by employing OpenMP and CUDA so that both GPU and multi-core CPU were utilized simultaneously. The two implementation schemes have been tested and compared with the sequential single threaded MC simulation on the CPU. A calculation time comparison was established on the speed-up for a set of benchmarking cases of electron and proton. Results: Dosimetric results were obtained with both the parallel and serial MC codes. A GPU over CPU speed-up of 67.2 and 19.2 times was achieved for 300 eV and 2 keV electron tracks respectively. For proton tracks, the GPU-based code was approximately 5 times faster than the CPU-single-thread code. By incorporating a multi-core CPU and running the MC code simultaneously on the GPU and CPU, an increase of 2%-7% and 20% in the speedup was noticed for electrons and protons tracks respectively. A good dosimetric agreement between the CPU- and GPU-based MC methods was observed for both electrons and proton. Conclusions: A GPU-based MC method for microdosimetric calculations of low energy electron and proton has been presented. The results indicate the capability of our GPU-based implementation for accelerated MC simulations of both electron and proton without loss of accuracy. Lastly, the potential of a hybrid approach by utilizing simultaneously a GPU and a multi-core CPU for further acceleration of MC microdosimetric calculations has been demonstrated.

The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric design space exploration for optimization, followed by design verification. Designers of special purpose VLSI implementations often need to explore parameters, such as optimal bitwidth and data representation, through time-consuming Monte Carlo simulations. A prominent example of this simulation-based exploration process is the design of decoders for error correcting systems, such as the Low-Density Parity-Check (LDPC) codes adopted by modern communication standards, which involves thousands of Monte Carlo runs for each design point. Currently, high-performance computing offers a wide set of acceleration options that range from multicore CPUs to Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs). The exploitation of diverse target architectures is typically associated with developing multiple code versions, often using distinct programming paradigms. In this context, we evaluate the concept of retargeting a single OpenCL program to multiple platforms, thereby significantly reducing design time. A single OpenCL-based parallel kernel is used without modifications or code tuning on multicore CPUs, GPUs, and FPGAs. We use SOpenCL (Silicon to OpenCL), a tool that automatically converts OpenCL kernels to RTL in order to introduce FPGAs as a potential platform to efficiently execute simulations coded in OpenCL. We use LDPC decoding simulations as a case study. Experimental results were obtained by testing a variety of regular and irregular LDPC codes that range from short/medium (e.g., 8,000 bit) to long length (e.g., 64,800 bit) DVB-S2 codes. We observe that, depending on the design parameters to be simulated, on the dimension and phase of the design, the GPU or FPGA may suit different purposes more conveniently, thus providing different acceleration factors over conventional multicore CPUs.

Low-density parity check (LDPC) codes with their near-Shannon capacity limit error correcting performance and iterative decoding algorithm are being evaluated for digital communications applications. For LDPC codes to be used in real systems, their error floors need to be investigated. In this paper, we evaluate the performance of disjoint difference set (DDS)-based LDPC codes (with column weights 3, 4, 5) and array code-based LDPC codes (with column weights 3, 4, 5) in the additive white Gaussian noise (AWGN) channel using a high-speed field programmable gate array (FPGA) simulation platform. The error floor regions (bit error rates down to 10/sup -12/) of those codes are presented. For better performance of array codes, a girth optimization method is proposed and the FPGA evaluation results are presented.

Coding Schemes for Energy Constrained IoT Devices

In Japan, the next generation of Integrated Services Digital Broadcasting — Terrestrial (ISDB-T) system is being developed for transmission of large-volume content services such as ultra high definition television (UHDTV). The system uses low density parity check (LDPC) code as the forward error correction (FEC) to improve its robustness. In particular, the performance of the system's FEC should be evaluated not only in additive white Gaussian noise (AWGN) environments, but also in multipath environments. Moreover, it would be desirable for the new FEC to have better performance than the previous one even in multipath environments. Previous research evaluated the transmission performance of LDPC code by using computer simulations of the propagation model. The actual propagation characteristics were not evaluated. In this paper, we describe the transmission performance of convolutional coded orthogonal frequency division multiplexing (CC-OFDM) and LDPC coded OFDM (LDPC-OFDM) in computer simulations using the same OFDM frame structure and propagation channels as measured in an outdoor experiment conducted in an urban area. We show that LDPC code outperforms CC in multipath environments and how the transmission performance depends on the code rate. In addition, we analyze the correlation between transmission performance and propagation channels.

Recently, there have been different applications, namely 10GBase-T Ethernet, video broadcasting and satellite communication, utilizing low-density parity-check (LDPC) codes as the forward-error-correction codes. The main reason is that the error performance of LDPC codes can be very close to the Shannon limit. LDPC codes can be further categorized into LDPC block codes (LDPC-BCs) and LDPC convolutional codes (LDPC-CCs). It has also been discovered that LDPC-CCs usually outperform LDPC-BCs. Simulation of LDPC-BCs and LDPC-CCs can take a lot of time because the decoding algorithms are relatively complex. Fortunately, the decoding steps can be performed in parallel. In this paper, we create three different platforms for simulating the error performance of LDPC-CCs. The first two platforms are run on a Central Processing Unit (CPU) while the third one involves the use of a Graphics Processing Unit (GPU). We show that using GPU can improve the simulation speed substantially.

Many algorithms for image processing and pattern recognition have recently been implemented on GPU (graphic processing unit) for faster computational times. However, the implementation using GPU encounters two problems. First, the programmer should master the fundamentals of the graphics shading languages that require the prior knowledge on computer graphics. Second, in a job which needs much cooperation between CPU and GPU, which is usual in image processings and pattern recognitions contrary to the graphics area, CPU should generate raw feature data for GPU processing as much as possible to effectively utilize GPU performance. This paper proposes more quick and efficient implementation of neural networks on both GPU and multi-core CPU. We use CUDA (compute unified device architecture) that can be easily programmed due to its simple C language-like style instead of GPU to solve the first problem. Moreover, OpenMP (Open Multi-Processing) is used to concurrently process multiple data with single instruction on multi-core CPU, which results ineffectively utilizing the memories of GPU. In the experiments, we implemented neural networks-based text detection system using the proposed architecture, and the computational times showed about 15 times faster than implementation using CPU and about 4 times faster than implementation on only GPU without OpenMP.

Previous studies that used Graphics Processing Units (GPUs) to decode Low Density Parity Check (LDPC) codes for DVB-S2 employed inter-codeword parallelism and/or Turbo Decoding Message Passing (TDMP) to achieve high throughput. By converting the LDPC parity check matrix into a quasi-cyclic structure, we show that LDPC encoding can be efficiently implemented on a GPU, and a different approach to LDPC decoding with intra-codeword parallelism and early termination that can achieve approximately 100 Mbps increase in throughput per 0.1 dB increase in signal-to-noise ratio and, for some cases, achieve 1 Gbps or greater overall throughput.

<strong class="journal-contentHeaderColor">Abstract.</strong> With semiconductor technology gradually approaching its physical and thermal limits, Graphics processing unit (GPU) is becoming an attractive solution in many scientific applications due to their high performance. This paper presents an application of GPU accelerators in air quality model. We endeavor to demonstrate an approach that runs a PPM solver of horizontal advection (HADVPPM) for air quality model CAMx on GPU clusters. Specifically, we first convert the HADVPPM to a new Compute Unified Device Architecture C (CUDA C) code to make it computable on the GPU (GPU-HADVPPM). Then, a series of optimization measures are taken, including reducing the CPU-GPU communication frequency, increasing the size of data computation on GPU, optimizing the GPU memory access, and using thread and block indices in order to improve the overall computing performance of CAMx model coupled with GPU-HADVPPM (named as CAMx-CUDA model). Finally, a heterogeneous, hybrid programming paradigm is presented and utilized with the GPU-HADVPPM on GPU clusters with Massage Passing Interface (MPI) and CUDA. Offline experiment results show that running GPU-HADVPPM on one NVIDIA Tesla K40m and NVIDIA Tesla V100 GPU can achieve up to 845.4x and 1113.6x acceleration. By implementing a series of optimization schemes, the CAMx-CUDA model resulted in a 29.0x and 128.4x improvement in computational efficiency using a GPU accelerator card on a K40m and V100 cluster, respectively. In terms of the single-module computational efficiency of GPU-HADVPPM, it can achieve 1.3x and 19.4x speedup on NVIDIA Tesla K40m GPU and NVIDA Tesla V100 GPU respectively. The multi-GPU acceleration algorithm enables 4.5x speedup with 8 CPU cores and 8 GPU accelerators on V100 cluster.