Leakage Power Attack-Resilient Design: PMOS-Reading 9T SRAM Cell

In terms of memory, multivalued logic can be the fitting logic for the existing binary logic. Ternary logic contains three symbols in place of two symbols used in the binary logic, i.e., 0, 1, 2. More information can be stored with the help of these three symbols. SRAM cell is widely used in the digital circuit. The SRAM cell designed using the ternary logic can be used in the design of large memory arrays designed using ternary logic. The traditional ternary inverter which is used in the design of the traditional ternary SRAM cell is unable to store the proper values for the second state, there is a voltage level drop, which in turn affects the data read/write value of the SRAM cell designed using this traditional ternary inverter. Hence there is a need to design the ternary inverter cell which can give the proper output voltage level of all three states of the ternary logic. The level shift ternary inverter is designed to fulfill this disadvantage. The ternary inverter is designed in order to achieve the ideal DC characteristics, and the same level shift ternary inverter is used in the design of level shift ternary SRAM. This ternary SRAM stores the data properly at read/write signal. The traditional ternary inverter and traditional ternary SRAM, level shift ternary inverter and level shift ternary SRAM are implemented in Cadence 45 nm technology. The traditional ternary inverter consumes 2.37 μW power, and the level shift ternary SRAM consumes 2.43 μW power. The traditional ternary SRAM consumes 3.012 μW and level shift ternary SRAM consumes 3.14 μW. At the cost of a little bit increased power and the number of transistors, the traditional ternary SRAM can be replaced with level shift ternary SRAM. This level shift ternary SRAM stores all the voltage levels at all three levels. The same level shift ternary SRAM cell can be used for the design of large memory arrays.

This paper proposes a novel low power 8T SRAM cell for write operation. In the proposed structure, two voltage sources VS1 and VS2 are connected with the bit line and the bit bar line, respectively. These voltage sources reduce the swing voltage and reduction in swing voltage causes the reduction in dynamic power dissipation of the proposed SRAM cell. Also, two different leakage power reduction techniques called upper self controllable voltage level (USVL) and lower self controllable voltage level (LSVL) have been proposed and applied individually and in combination with the proposed 8T SRAM for the reduction of leakage current. Both the leakage current and power dissipation results are compared with those of conventional 6T and 7T SRAM cells reported in different literatures. Static noise margin is also analysed during write operation for stability purpose. The proposed SRAM cell has lesser leakage current in comparison to conventional 6T SRAM cell and also dissipates the least amount of power and yields better stability in comparison to both 6T and 7T SRAM cells. The authors use 45 nm CMOS technology with 0.5 volt power supply for simulation purpose. Microwind 3.1 software is used for schematic design and simulation.

Design of improved write and read performance 12T sram cell with leakage power control technique

There are severe constraints which affect the real time operation of SRAM cells. With increasing demand of device scaling, the performance parameters of SRAM cells are affected. Our main purpose is to maintain performance of memory cells in real time operation. Here, we considered three basic parameters stability, leakage current and delay for compression of various SRAM cell architectures. In this paper, we considered conventional 6T, asymmetric 7T, asymmetric 8T and asymmetric 9T SRAM cells and calculated various design parameters using simulation of mentioned circuits at 70 nm. Here, to find better parametric compression, different cell ratios were also considered. From the simulation results, it is found that using MTCMOS design techniques, leakage current is effectively suppressed but on account of delay penalty. The delay penalty can also be minimized by selecting properly sized inverter cell. Keywords: SRAM, stability, SNM, MTCMOS Cite this Article Nidhi Tiwari, Vaibhav Neema, Rangra Kamal J et al. Comparative Analysis of Different SRAM Cells Architecture at 70 nm. Journal of VLSI Design Tools & Technology. 2018; 8(2): 33–41p.

Cryptography is essential to ensure data security in embedded devices that handle sensitive data. SRAM boosts overall performance by temporarily storing cryptographic keys. However, attackers can use side-channel, such as Power Analysis, to exploit power consumption patterns and extract secret keys. Once a key is compromised, encrypted data becomes vulnerable. There are many secure SRAM cell designs available in the literature, but they often degrade other performance parameters. This article presents a novel 10-T SRAM cell design that provides protection against power analysis side-channel attacks (SCA) across all three cell operations, while also maintaining the performance of other key parameters. Monte Carlo simulations were conducted on 1,000 samples each for case when BL = Q and BL ≠ Q during reading, writing, and holding data, using Cadence Virtuoso with a 45-nm technology node at 1V/270°C. Based on these simulations, the mean power difference was evaluated. The proposed P-10T SRAM cell exhibits a 0% mean power difference in all three modes of operation, demonstrating complete resilience to power analysis SCA. The design achieves 84.87% reliability with hold stability, read stability, and write ability values of 429 mV, 242 mV, and 250 mV, respectively. Furthermore, the write power dissipation of P-10T cell is 57.44 μW, which is 1.80 × lower than the power consumed by the conventional 6T cell.

The demand for enhancing the performance of reliable processors necessitates using dependable, energy-efficient, and high-speed memory. Multiple obstacles arise as a consequence of this enhancement at lower technological nodes. Process, voltage, and temperature fluctuation significantly influence several performance characteristics, making it a crucial concern in nanometer SRAM design. This study presents two novel SRAM designs that effectively decrease power consumption during read operations without compromising performance or stability. A 14T SRAM has been built with an architecture that enables single-ended write and differential read operations. In addition, a 13T SRAM has been developed using an architecture that incorporates a differential write and single-ended read operation with the assistance of a write-read circuit. The two suggested SRAM cells have been fabricated using the CMOS 45 nm technology. The provided study examines the impact of modifications in process parameters on several design metrics, including the proposed cell's read-write power and current. These metrics are then compared with those of a previously suggested SRAM cell. The read power consumption of the 14T SRAM cell is reduced by 20 %, 60.63 %, 34.73 % 53.68 %, when compared to CS6T, SS8T, SS10T, and SEW10T. For the proposed 13T SRAM, the read power consumption is reduced by 147.40 %, 230.43 %, 178.2 % 217.39 %, 30.4 % when compared to CS6T, SS8T,SS10T, SEW10T, SER11T. Also the proposed SRAM II has 106.52 % lower read power when compared with proposed 14T SRAM. Also the write power of the proposed 13T SRAM is at lower side when compared to others but at the sametime write power of proposed 14T suffers from higher power consumption. Therefore the proposed 13T SRAM has been considered for the further evaluation. The RSNM and WSNM show atleast 5 % improvement when compared to existing architectures.

In this paper, we have proposed a novel low power Finfet based Sram cell design which has different read access path and write access path. The proposed cell achieves better performance compared to conventional sram cell. Proposed cell achieves 78% for hold 1 and 67% for hold 0 static power reduction than conventional 8T and 6T Sram cell. The proposed sram cell achieves 69% and 58% for write performance in terms of power and delay. Read delay is also reduced by approximately 89% and read power is reduced by 87%. Compared to conventional 8T Sram Cell. The proposed cell is read SNM free and has better SNM for write compared to Conventional Sram Cell.

In this work one-transistor static random access memory cell (SRAM) to reduce power consumption using tunnel diode as basic latching circuit element is designed and simulated. The SRAM cell consists of a transistor (nMOSFET) having effective gate length of 18nm and a pair of Si-Ge Tunnel diode having current peak to valley current ratio (PVR) of value 1.67 each. The bistability of the back-to-back series connected tunnel diode pair is used to hold the states of the designed SRAM cell and the pass transistor is used to control the switching of the tunnel diode. The changing in the state of the designed SRAM is observed by the variation of drain current (ID) of the transistor. This SRAM cell highly reduces the power dissipation compared to conventional SRAM cell and other SRAM cell structures.

Leakage current consumes the majority of the active mode energy in the high-performance integrated circuits of today. In particular, in high microprocessor and system-on-chip architectures, the SRAM cell array is the primary source of leakage current. So low-leakage SRAM design is essential. Today’s VLSI designs are all about cutting down on power dissipation, supply voltage, leakage currents, and chip area. However, raising these parameters increases sub-threshold leakage currents and power dissipation, reducing design performance. Increasing the cell area reduces leakage power dissipation in standby mode. To solve these problems, it is best to cut down on effective leakage currents and dynamic power dissipation. For low voltage and energy constraints, the power dissipation, area, and delay performance of the low-power design of the 6T-SRAM cell with the DTMOS technique for a proposed low-power SRAM will be implemented in the Tanner EDA tool in 22 nm technology. The power of both types of SRAM cells will be compared using low-power techniques and a power analysis.

This paper explores a low standby power 10T (LP10T) SRAM cell with high read stability and write-ability (RSNM/WSNM/WM). The proposed LP10T SRAM cell uses a strong cross-coupled structure consisting standard inverter with a stacked transistor and Schmitt-trigger inverter with a double-length pull-up transistor. This along with the read path separated from true internal storage nodes eliminates the read-disturbance. Furthermore, it performs its write operation in pseudo differential form through write bitline and control signal with a write-assist technique. To estimate the proposed LP10T SRAM cell’s performance, it is compared with some state-of-the-art SRAM cells using HSPICE in 16-nm CMOS predictive technology model at 0.7 V supply voltage under harsh manufacturing process, voltage, and temperature variations. The proposed SRAM cell offers 4.65X/1.57X/1.46X improvement in RSNM/WSNM/WM and 4.40X/1.69X narrower spread in RSNM/WM compared to the conventional 6T SRAM cell. Furthermore, it shows 1.26X/1.08X/1.01X higher RSNM/WSNM/WM and 1.71X/1.25X tighter/wider spread in RSNM/WM compared to the best studied SRAM cells. The proposed SRAM cell indicates 74.48%/1.41% higher/lower read/write delay compared to the 6T SRAM cell. Moreover, it exhibits the third-(second-) best read (write) dynamic power, consuming 29.69% (26.87%) lower than the 6T SRAM cell. The leakage power is minimized by the proposed design, which is 37.35% and 12.08% lower than that of the 6T and best studied cells, respectively. Nonetheless, the proposed LP10T SRAM cell occupies 1.313X higher area compared to the 6T SRAM cell.

In nanoscale SRAM design, issues related to cell stability, power dissipation, and delay are increasingly critical in the nanoscale SRAM design due to aggressive scaling of technology geometries. This paper presents a low-power and high-performance 8T SRAM cell design based on CNTFET technology for aerospace applications and the input-dependent (INDEP) technique. The proposed design addresses critical challenges in nanoscale SRAM, including high leakage currents, power dissipation, and stability issues. This architecture in comparison to conventional 6T and 12T SRAM cells brings notable performance gains. Superior stability is ensured by a read SNM of 402.5 mV, hold SNM of 402.2 mV, and write SNM of 423.6 mV. The design also shows faster operations, with a write time of 1.3 ns and read time of 1.8 ns, while maintaining energy efficiency with reduced read energy (18 aJ) and write energy (22 aJ). The static power consumption is also reduced to 0.7 µW with a considerable improvement compared with the traditional architectures. This work has set the basis for the 8T INDEP-CNTFET SRAM cell as an upcoming choice for next-generation energy-efficient memory applications in modern VLSI systems. Additionally, WSNM write access time is improved along with read access speed, which decreases and energy efficiency increases. These make the proposed 8T INDEP-CNTFET SRAM cell one of the promising solutions for future nanoscale memory applications.

As technology scales, Negative Bias Temperature Instability (NBTI) has become a major reliability concern for circuit designers. And the growing process variations can no longer be ignored. Meanwhile, reducing leakage power remains to be one of the design goals. In this paper, we first present a platform for NBTI-aware statistical timing and leakage power analysis. A variation-aware supply voltage assignment (SVA) technique combining dual Vdd assignment and dynamic Vdd scaling techniques is proposed to minimize NBTI degradation and leakage. Based on the statistical platform, we analyze the impact of Vth variations on NBTI degradation and leakage. The experimental results show that our SVA technique can mitigate on average 52.98% of NBTI degradation with little or without leakage power increase; furthermore, it can reduce on average 32.46% more leakage power compared with the pure single Vdd scaling technique. Compared with scheduled voltage scaling technique [9], our dynamic scaling technique is more effective because the circuit delay will exactly meet the specification at each dynamically decided time node during circuit operation.

Analysis of the impact of spatial and temporal variations on the stability of SRAM arrays and the mitigation technique using independent-gate devices

PurposeMajor area of a die is consumed in memory components. Almost 60-70% of chip area is being consumed by “Memory Circuits”. The dominant memory in this market is SRAM, even though the SRAM size is larger than embedded DRAM, as SRAM does not have yield issues and the cost is not high as compared to DRAM. At the same time, the other attractive feature for the SRAM is speed, and it can be used for low power applications. CMOS SRAM is the crucial component in microprocessor chips and applications, and as the said major portion of the area is dedicated to SRAM arrays, CMOS SRAM is considered to be the stack holders in the memory market. Because of the scaling feature of CMOS, SRAM had its hold in the market over the past few decades. In recent years, the limitations of the CMOS scaling have raised so many issues like short channel effects, threshold voltage variations. The increased thrust for alternative devices leads to FinFET. FinFET is emerging as one of the suitable alternatives for CMOS and in the region of memory circuits.Design/methodology/approachIn this paper, a new 11 T SRAM cell using FinFET technology has been proposed, the basic component of the cell is the 6 T SRAM cell with 4 NMOS access transistors to improve the stability and also makes it a dual port memory cell. The proposed cell uses a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability thus, helps in reducing the leakage power and active power.FindingsThe cell shows improvement in RSNM (read static noise margin) with LP8T by 2.39× at sub-threshold voltage 2.68× with D6T SRAM cell, 5.5× with TG8T. The WSNM (write static noise margin) and HM (hold margin) of the SRAM cell at 0.9 V is 306 mV and 384 mV. It shows improvement at sub-threshold operation also. The leakage power is reduced by 0.125× with LP8T, 0.022× with D6T SRAM cell, TG8T and SE8T. The impact of process variation on cell stability is also discussed.Research limitations/implicationsThe FinFet has been used in place of CMOS even though the FinFet has been not been a matured technology; therefore, pdk files have been used.Practical implicationsSRAM cell has been designed which has good stability and reduced leakage by which we can make an array and which can be used as SRAM array.Social implicationsThe cell can be used for SRAM memory for low power consumptions.Originality/valueThe work has been done by implementing various leakage techniques to design a stable and improved SRAM cell. The advantage of this work is that the cell has been working for low voltage without degrading the stability factor.

Optimized threshold voltage (Vt) design to enhance the variation immunity of high-performance (super-threshold) and low-voltage (near-/sub-threshold) 6 T SRAM cells is presented. For low-voltage SRAM cells operating at low Vdd, low-Vt design shows smaller variability, while the design tradeoff between performance and leakage should be considered. For high-performance SRAM cells operating at high Vdd, ultra-thin-body SOI SRAM cells with high-Vt design show smaller variability while sacrificing performance compared with the low-Vt design. Our study indicates that hetero-channel SRAM cells enable high-Vt design and exhibit improved Read/Write stability and performance, and maintain comparable RSNM variations for the high-performance SRAM applications.