Learning Applied to Successive Approximation Algorithms

An asynchronous 6 bit 1 GS/s ADC is achieved by time interleaving two ADCs based on the binary successive approximation (SA) algorithm using a series capacitive ladder. The semi-closed loop asynchronous technique eliminates the high internal clocks and significantly speeds up the SA algorithm. A key feature to reduce the power in this design involves relaxing the comparator requirements using an error correction technique, which can be viewed as an extension of the SA algorithm to remove degradation due to metastability. Fabricated in 65 nm CMOS with an active area of 0.11 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , it achieves a peak SNDR of 31.5 dB at 1GS/s sampling rate and has a total power consumption of 6.7 mW.

Two-stage stochastic optimization, in which a long-term master problem is coupled with a family of short-term subproblems, plays a critical role in various application areas. However, most existing algorithms for two-stage stochastic optimization only work for special cases, and/or are based on the batch method, which requires huge memory and computational complexity. To the best of our knowledge, there still lack efficient and general two-stage online stochastic optimization algorithms. This paper proposes a two-stage online successive convex approximation (TOSCA) algorithm for general two-stage nonconvex stochastic optimization problems. At each iteration, the TOSCA algorithm first solves one short-term subproblem associated with the current realization of the system state. Then, it constructs a convex surrogate function for the objective of the long-term master problem. Finally, the long-term variables are updated by solving a convex approximation problem obtained by replacing the objective function in the long-term master problem with the convex surrogate function. We establish the almost sure convergence of the TOSCA algorithm and customize the algorithmic framework to solve three important application problems. Simulations show that the TOSCA algorithm can achieve superior performance over existing solutions.

Intelligent reflecting surface (IRS)-aided wireless relaying system has aroused great interest recently due to its potential to improve the relaying performance. However, most existing works only consider the decode-and-forward (DF) relay and ignore the base station (BS) to user direct link. In this paper, we focus on an IRS-aided full-duplex (FD) amplify-and-forward (AF) relay system and study the beamforming optimization problem. Specifically, we aim to maximize the transmission rate when deploying the IRS near the relay by jointly optimizing the IRS reflection coefficients and transmit powers at the BS and relay. Then, a virtual stochastic successive convex approximation (VSSCA) algorithm is developed to solve our formulated de-terministic optimization problem efficiently. Finally, numerical results are provided to demonstrate the effectiveness of our proposed algorithm as compared to various benchmark schemes.

Benefiting from the rapid development of metamaterials and metasurfaces, the holographic multiple-input and multiple-output surface (HMIMOS) has been regarded as a promising solution for future wireless networks recently. By densely packing numerous radiation elements together, HMIMOS is capable of realizing accurate beamforming with low hardware complexity. However, enormous radiation elements on the HMIMOS lead to high computational complexity and signaling overhead when applying traditional beamforming schemes relying on instantaneous channel state information (CSI). To tackle this problem, we propose a two-timescale optimization scheme to minimize the required transmission power under the constraint of all users' quality-of-service (QoS). Specifically, the beampatterns at the base station (BS) and the user equippment (UE) are optimized over the slowly changing statistical CSI based on the constrained stochastic successive convex approximation (CSSCA) algorithm. Then, the instantaneous CSI is utilized to design the precoding matrix in order to ensure the system performance without significant increase in computational cost, due to the small number of feeds on the HMIMOS. Simulation results demonstrate the effectiveness of our proposed method compared to other baselines.

Both the power-dissipation and cost of massive multiple-input multiple-output (mMIMO) systems may be substantially reduced by using low-resolution analog-to-digital converters (LADCs) at the receivers. However, both the coarse quantization of LADCs and the inaccurate instantaneous channel state information (ICSI) degrade the performance of quantized mMIMO systems. To overcome these challenges, we propose a novel stochastic hybrid analog-digital combiner (SHC) scheme for adapting the hybrid combiner to the long-term statistics of the channel state information (SCSI). We seek to minimize the transmit power by jointly optimizing the SHC subject to average rate constraints. For the sake of solving the resultant nonconvex stochastic optimization problem, we develop a relaxed stochastic successive convex approximation (RSSCA) algorithm. Simulations are carried out to confirm the benefits of our proposed scheme over the benchmarkers

Stochastic approximation algorithms with non-additive noise are discussed. In studying strong convergence of such algorithms, traditionally one assumes that the iterates return to a bounded or compact set infinitely often, or that the function under consideration grows with certain rate. The usual projection algorithms require that the bounded projection region is known beforehand. It is desirable to weaken these ‘boundedness’ conditions. By introducing randomly varying truncations, Chen and Zhu (1986) achieved this for stochastic approximation algorithms with additive noise. Here, we extend their result to a more general setting.

We study four conditions on noise sequences for convergence of stochastic approximation algorithms on a general Hilbert space: Kushner and Clark's condition (1978), Chen's condition (1994), Kulkarni and Horn's condition (1995), and a decomposition condition. We discuss various properties of these conditions. In our main result we show that the four conditions are all equivalent, and are both necessary and sufficient for convergence of stochastic approximation algorithms under appropriate assumptions.

It has been previously shown by Kohonen and others how a linear system can be trained to associate two deterministic pattern sets, with applications to learning algorithms and adaptive systems. When noise is added to the training patterns, the algorithm is close to stochastic approximation algorithms with constant gain. Some results are given here concerning the convergence of the algorithm with different assumptions on the training pattern statistics and the gain, and a stochastic counterpart is given to the basic deterministic algorithm in case an exact association exists. It is established how the non-zero residual error, resulting from a gain sequence not tending to zero, can be made arbitrarily small using redundancy. It is also shown how the optimal associative mapping in the noisy case is related to the basic mapping reported earlier.

The work proposes an improved technique to design a low power 8-bit asynchronous successive approximation register (ASAR), an analog-to-digital converter (ADC). The proposed ASAR ADC consists of a comparator, ASAR (digital control logic block), and a capacitive-digital-to-analog convertor (C-DAC). The comparator is a preamplier-based improved positive feedback latch circuit which has a built-in sample and hold (S/H) functionality and saves an enormous amount of power. The implemented digital control logic block performing the successive approximation (SA) algorithm is totally unrestrained of the external clock pulse. The outputs from the comparator are given to a XOR logic whose outputs serve as an internally generated clock (ready signal) to trigger the digital control block. Hence, an external clock is not required to initiate the digital control block making its operation asynchronous. By implementing this, the ADC can circumvent the usage of an oversampled clock and can operate on a single low-speed sample clock. This, in turn, saves power and it cuts down the required resilience in sampling rates. The proposed ADC has been designed and simulated using UMC-0.18[Formula: see text][Formula: see text]m CMOS technology which dissipates 32.18[Formula: see text][Formula: see text]W power when operated on a single 1[Formula: see text]V power supply and achieves complete 8-bit conversion in 1.09[Formula: see text][Formula: see text]s. The relative accuracy of capacitor ratio, aperture jitter and FOM are 0.39[Formula: see text], 1.2[Formula: see text]ns and 125[Formula: see text]fJ/conversion-step, respectively.

This paper presents a 10-bit 100MS/s analog to digital converter (ADC) that based on successive approximation (SAR) algorithm. This ASIC is to fulfill the requirement of Hadronic Calorimeter (HCal) upgrade: custom cost-efficient high sampling digitizer electronics and capable of continuous operation mode. The designed chip is developed by using the TSMC 65nm CMOS technology. The post-layout simulations show this ADC could achieve peak signal to noise and distortion ratio (SNDR) of 58 dB at Nyquist rate input frequency and power consumption of 3.5 mW. The peak effective number of bits (ENOB) is 9.6 bits, equivalent to the figure of merit of 45 fJ/conversion step.

Robust optimization for AN-aided wireless information and power transfer for secure heterogeneous networks

Integrating reconfigurable intelligent surface (RIS) and non-orthogonal multiple access (NOMA) provides a promising solution to support large-scale secure communications. However, reducing the impact of transceiver hardware impairments (HWI) on the performance of RIS-aided NOMA secure networks remains a challenge. In this paper, we propose a robust transmission scheme for RIS-aided NOMA secure networks with transceiver HWI under two proposed eavesdropping scenarios and two artificial noise methods. A closed-form expression for the distortion noise power caused by transceiver HWI in NOMA networks is derived to quantify transceiver HWI. The sum secrecy rate of NOMA users with imperfect successive interference cancellation (SIC) is maximized under distortion noise for more robust security. Further, to tackle the resulting non-convex problem, we decompose it into two sub-problems. Both of them are converted into convex problems using the multi-dimensional quadratic transform (MDQT) method, semi-definite relaxation (SDR) technique, and the successive convex approximation (SCA) algorithm, and then employing the alternate optimization (AO) algorithm solve them. Numerical results demonstrate that the proposed scheme has superior security performance over orthogonal multiple access (OMA) networks, time division multiple access (TDMA) networks, and traditional NOMA networks, achieving more robust performance than the conventional scheme that ignores HWI and imperfect SIC.

Minimizing energy consumption in UAV assisted NOMA-MEC networks

Due to its flexible deployment and high mobility of unmanned aerial vehicles (UAVs), the UAV-assisted cognitive radio (CR) network has attracted a lot of attention as one of the most promising techniques to address spectrum congestion issues in futuristic networks. However, its performance can be severely affected by the blocked line-of-sight (LoS) channel in its air-to-ground (A2G) links. In this paper, we propose a UAV CR system enabled by a reconfigurable intelligent surface (RIS), which helps to reconstruct reliable links in UAV-assisted cognitive radio (CR) networks. Our goal is to maximize the achievable rate of a secondary receiver (SR) through the proper selection of the UAV trajectory, transmit power, and RIS phase shifts based on a given interference temperature threshold and other practical constraints. In addition, we solve the corresponding non-convex optimization problem using block coordinate descent (BCD) and successive convex approximation (SCA) algorithms. The simulation results will demonstrate the effectiveness of the proposed algorithms.

Recently, unmanned aerial vehicle (UAV) has been considered as a promising technique in mobile edge computing networks, and enhances the performances of ultra-reliable and low-latency services. In this paper, we propose a UAV-aided low latency mobile edge computing network with millimeter wave (mmWave) backhaul. There are two types of communication links in our network, the UAV link and the ad hoc link. We jointly consider the network resource allocation and the UAV trajectory design in our proposed problem, which is a non-convex mixed integer nonlinear programming (MINLP). For solving the proposed problem, we give a novel algorithm framework. We adopt generalized Benders decomposition (GBD) as the outer loop algorithm to separate the integer variables and continuous variables. In the inner loop, the continuous primal problem is solved by the joint alternating direction method of multipliers (ADMM), Dinkelbach algorithm and successive convex approximation (SCA) algorithm. The simulation results show that our proposed system architecture and algorithm framework can achieve low latency for the time-sensitive task in mobile edge computing.