Learning from constraints for formal property checking

Constraints are commonly used in both simulation and formal verification in order to specify expected input conditions and state transitions. Constraint solving is a process to determine input vectors which satisfy the set of constraints during constrained random simulation. Even though constraints are used in formal property checking to restrict the search space, constraint solving has never had direct application to formal property checking. There are often many simple, yet powerful, invariants that can be learned from constraint solving during constrained random simulation. These invariants are shown in this paper to significantly simplify the formal verification problem. We use approximate constraint solving to compute an approximate set of valid input vectors. The approximate set of valid input vectors are a strict superset of the set of all legal input vectors. We use BDD techniques to compute these input vectors during constrained random simulation, then process the resulting BDDs for learning invariants which can be used during formal property checking. This paper presents efficient BDD algorithms to learn invariants from the BDDs generated from approximate constraint solving. We also present how these learned invariants can be applied to the formal property checking. Experimental results show that invariants learned during constraint solving can significantly improve the performance of formal property checking with many industrial designs.

The condition-based approach to solve consensus has initially been developed in the context of asynchronous systems. It identifies a class of acceptable conditions on the set of input vectors that, when satisfied by the actual input vector, are exactly the conditions that allow to solve consensus despite up to t faulty processes. This paper investigates the use of conditions to solve consensus in synchronous systems prone to process crash failures. It first shows that for any acceptable condition there is a condition-based protocol solving uniform consensus that enjoys the following property: when the input vector belongs to the condition, it terminates in a single round if no process crashes, and in two rounds otherwise. When the input vector does not belong to the condition, the actual number of rounds is upper bounded by t+1 (it actually depends on both the crash pattern and the input vector). The paper then extends the previous protocol to combine early decision with the condition-based approach. It presents a general protocol that enjoys the previous properties (decision in one or two rounds) when the input vector belongs to the condition and terminates in at most (t + 1, f + 2) rounds when the input vector does not belong to the condition (where f is the actual number of faulty processes). Finally, the paper presents corresponding matching lower bounds. It shows that acceptable conditions are the only ones for which a consensus protocol can enjoy the previous properties.

We describe a new approach to test generation for stuck-at faults in synchronous sequential circuits. Under this approach, the input vectors comprising the test sequence are fixed in advance. The process of generating the test sequence consists of ordering the precomputed input vectors such that the resulting test sequence has as high a fault coverage as possible. The advantage of this approach is that its computational complexity is limited by limiting the search space to a given set of input vectors and a given test sequence length. We describe a specific implementation of this approach. Experimental results demonstrate that restricting the search space to a fixed number of precomputed input vectors is sufficient for achieving the highest known fault coverage, or a fault coverage close to it, for benchmark circuits.

We demonstrate that a program synthesis approach based on a linear code representation can be used to generate algorithms that approximate the ground-state solutions of one-dimensional time-independent Schrödinger equations constructed with bound polynomial potential energy surfaces (PESs). Here, an algorithm is constructed as a linear series of instructions operating on a set of input vectors, matrices, and constants that define the problem characteristics, such as the PES. Discrete optimization is performed using simulated annealing in order to identify sequences of code-lines, operating on the program inputs that can reproduce the expected ground-state wavefunctions ψ(x) for a set of target PESs. The outcome of this optimization is not simply a mathematical function approximating ψ(x) but is, instead, a complete algorithm that converts the input vectors describing the system into a ground-state solution of the Schrödinger equation. These initial results pointthe way toward an alternative route for developing novel algorithms for quantum chemistry applications.

STAtistical Fault ANalysis (STAFAN) is proposed as an alternative to fault simulation of digital circuits. In this analysis, controllabilities and observabilities of circuit nodes are defined as probabilities which are estimated from signal statistics obtained from fault-free simulation. Special procedures are developed for dealing with these quantities at fanout nodes and at feedback nodes. The computed probabilities are used to derive unbiased estimates of fault detection probabilities and overall fault coverage for the given set of input vectors. Fault coverage and the undetected fault data obtained from STAFAN for actual circuits are shown to agree favorably with the fault simulator results. The computational complexity added to a fault-free simulator by STAFAN grows only linearly with the number of circuit nodes.

A parallel growing architecture for self-organizing maps with unsupervised learning

During the test mode of flip flop in a chip, a set of input vectors are sent through the flip-flop, it consumes more power consumption than in the normal functional mode. In this paper, we propose a latch with bi -stable element which reduces area as well as the power consumed. The latch proposed consists of simple basic gates involving two inverters back to back which acts as a bi-stable element and a transmission gate with the clock signal used to enable and disable the rest of the circuit with impact on running the latch on Static Timing Analysis. The input test vectors are either given by Automatic Test Pattern Generation (ATPG) or many other methods. We model this using T-Simulation Program with Integrated Circuit Emphasis (T-SPICE) and see the power consumed.

The design of vector quantizers (VQs) that yield minimal distortion is one of the most challenging problems in source coding. The problem of VQ design is to find a codebook that gives the least overall distortion (or equivalently, the largest signal-to-noise ratio (SNR)) for a given set of input vectors. This problem is known to be difficult as there are no known closed-form solutions. The generalized Lloyd algorithm (GLA) uses a finite set of training sequences as the data source and employs an iterative refinement. Given an initial codebook, the algorithm computes the nearest focally optimum codebook only. Genetic algorithms (GAs) are emerging as widely accepted optimization and search methods. These search methods are rooted in the mechanisms of evolution and natural genetics. They have a high probability of locating the globally optimal solution in a multimodal search space. A genetic algorithmic (GA) approach to vector quantizer design that combines the GLA is presented. We refer to this hybrid as the genetic generalized Lloyd algorithm (GGLA). It works briefly as follows. Initially, a finite number of codebooks, called chromosomes, are selected. In contrast to the GLA which refines only one codebook at a time, those codebooks undergo iterative cycles of reproduction in parallel. During an iteration, each codebook is updated by GLA or GA operations (i.e., mutation, crossover, and chromosome replacement). Three versions of the GGLAs are investigated depending on how the GLA or GA is selected.

The article discusses the possibilities of using artificial intelligence systems to solve clustering problems. The value of the optimality criterion for various combinations of the number of clusters and the number of neurons of the output network layer is determined. Self-organizing maps (SOM, Self Organizing Maps), developed by T. Kohonen and representing a powerful tool combining two important paradigms of data analysis - clustering and projecting, visualization of multidimensional data on a plane are considered. An example of the location of cluster nuclei after training the Kohonen neural network for different values of the number of neurons in the source layer is given. Comparing the speed of modern computers with the speed of the Kohonen neural network, with other types of neural networks, allows you to conduct a large number of network exercises in a short time, so you can use one of many methods to determine the maximum value of the function. The results of experimental studies to determine the criterion of optimality are presented in the article for different combinations of the number of clusters and the number of neurons in the original layer of the network. According to the method at the initial stage, a set of input vectors is formed, each of which includes three values. A general sequence of actions is formulated to calculate the optimal number of neurons in the output layer of the Kohonen network. The methodology presented in the article is a further development of teaching methods without a teacher. The technique proposed in the article avoids the need to specify the number of outputs of the Kohonen neural network and can be widely used both in solving data mining problems and in recognizing new unknown classes and situations in different fields.

STAtistical Fault ANalysis (STAFAN) is proposed as an alternative to fault simulation of digital circuits. In this analysis, controllabilities and observabilities of circuit nodes are defined as probabilities which are estimated from signal statistics obtained from fault-free simulation. Special procedures are developed for dealing with these quantities at fanout nodes and at feedback nodes. The computed probabilities are used to derive unbiased estimates of fault detection probabilities and overall fault coverage for the given set of input vectors. Fault coverage and the undetected fault data obtained from STAFAN for actual circuits are shown to agree favorably with the fault simulator results. The computational complexity added to a fault-free simulator by STAFAN grows only linearly with the number of circuit nodes.

Many techniques for quantizing large sets of input vectors into much smaller sets of output vectors have been developed. Various neural network based techniques for generating the input vectors via system training are studied. The variations are centered around a neural net vector quantization (NNVQ) method which combines the well-known conventional Linde, Buzo and Gray (1980) (LBG) technique and the neural net based Kohonen (1984) technique. Sequential and parallel learning techniques for designing efficient NNVQs are given. The schemes presented require less computation time due to a new modified gain formula, partial/zero neighbor updating, and parallel learning of the code vectors. Using Gaussian-Markov source and speech signal benchmarks, it is shown that these new approaches lead to distortion as good as or better than that obtained using the LBG and Kohonen approaches.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Test generation for hard-to-reach states is important in functional verification. In this paper, we present a path constraint solving-based test generation method (PACOST) which operates in an abstraction-guided semiformal verification framework to cover hard-to-reach states. PACOST combines concrete simulation and symbolic simulation on the design under verification for path constraint extraction and mutation, and uses a sequential path constraint extractor to generate a set of valid input vectors for exploring different simulation paths with different next states. It then works on a target state-oriented abstract model to select the next state with the smallest abstract distance. In addition, the value of register variables in control logic can be controlled by analyzing the data dependence between variables, which helps the simulation converge to the target states. Experimental results show that PACOST can generate shorter traces reaching hard-to-reach states, in comparison with previous abstraction-guided semiformal methods.

An orthogonalised Volterra system model, valid for both non-Gaussian and Gaussian inputs, is presented. The approach is based on ordered sets of conditioned orthogonal higherorder input vectors in the frequency domain, and utilises co-ordinate transformation to relate the orthogonal and nonorthogonal system models. The orthogonal model exhibits no interference effects, thus facilitating physical interpretation of the nonlinear system model. The importance of non-Gaussian excitation in the nonlinear system identification procedure is discussed. The performance of the orthogonalised Volterra model is measured in terms of a generalised nonlinear system coherence function, and compared with the results of the Wiener (for Gaussian input) and Volterra models. The advantages of the orthogonalised Volterra model are illustrated by using it to model the linear and quadratic responses of a tension leg platform subject to random seas, given experimental input-output time series data.

This paper introduces a neural network approach to node placement in an arbitrarily shaped rectilinear boundary based on self-organising principle. An abstract specification of the design is converted to a set of appropriate input vectors fed to the network at random. At the end of the process, the map shows the rectilinear shape 2-dimensional plane of the design in which the modules with higher connectivity to each other and also to some external ports are placed close to each other, hence minimising total connection length in the design.

A wide variety of problems, ranging from planning and scheduling tasks in industry to making autonomous decisions in smart environments, can be modelled as constraint satisfaction problems (CSPs). While this general mathematical framework facilitates the reuse of algorithms for many different types of problems, the fact that CSPs are NP-complete gives them an exponential worst-case computational complexity. This complexity imposes severe restrictions on the size of the problem, as virtually all applications require problems to be solved in a timely fashion. However, despite being NP-complete problems, CSPs can often be solved efficiently in practice, making this worst-case complexity largely uninformative. The structure of a problem and of the search space have been used to identify classes of tractable problems and design more efficient solving techniques with better theoretical guarantees. Unfortunately, the worst-case bounds of these algorithms are hardly more informative when it comes to their practical efficiency, and exploiting this structure is challenging because efficient algorithms do not exist for many related tasks. This dissertation studies the structure of problems and their search space and how these influence the search times of algorithms. It provides additional insights into the computational complexity and practical efficiency of search algorithms, which can, for instance, be used to select the best algorithm for a given problem and aid in the design of more efficient solving techniques. This work also contributes towards improving the solving efficiency more directly by proposing improved ways to exploit the structure of a problem and the search space algorithmically.