Lithography at 14nm and beyond

Through the four years of study in Association of Super-Advanced Electronics Technologies (ASET) on reducing mask manufacturing Turn Around Time (TAT) and cost, we have been able to establish a technology to improve the efficiency of the review process by applying a printability verification function that utilizes computational lithography simulations to analyze defects detected by a high-resolution mask inspection system. With the advent of Source-Mask Optimization (SMO) and other technologies that extend the life of existing optical lithography, it is becoming extremely difficult to judge a defect only by the shape of a mask pattern, while avoiding pseudo-defects. Thus, printability verification is indispensable for filtering out nuisance defects from high-resolution mask inspection results. When using computational lithography simulations to verify printability with high precision, the image captured by the inspection system must be prepared with extensive care. However, for practical applications, this preparation process needs to be simplified. In addition, utilizing Mask Data Rank (MDR) to vary the defect detection sensitivity according to the patterns is also useful for simultaneously inspecting minute patterns and avoiding pseudo-defects. Combining these two technologies, we believe practical mask inspection for next generation lithography is achievable. We have been improving the estimation accuracy of the printability verification function through discussion with several customers and evaluation of their masks. In this report, we will describe the progress of these practical mask verification functions developed through customers' evaluations.

Mask manufacturers will be impacted by two significant technology requirements at 22nm and below: The first is more extensive use of resolution enhancement technologies (RET), such as OPC or Inverse Lithography Technology (ILT), and Source Mask Optimization (SMO); the second is EUV technology. Both will create difficulties for mask inspection, defect disposition, metrology, review, and repair. For example, the use of ILT and SMO significantly increases mask complexity, making mask defect disposition more challenging than ever. EUV actinic inspection and AIMS^TM will not be available for at least a few years, which makes EUV defect inspection and disposition more difficult, particularly regarding multilayer defects. Computational Lithography and Inspection (CLI), which has broad applications in mask inspection, metrology, review, and repair, has become essential to fill this technology gap. In this paper, several such CLI applications are presented and discussed.

Mask fabrication is one of the difficult challenges with all Next Generation Lithography (NGL) technologies. X-ray, e-beam projection, and ion-beam projection lithography all use some form of membrane mask, and extreme ultraviolet (EUV) lithography uses a reflective mask. Despite some differences, the various mask technologies share some common features and present similar fabrication difficulties. Over the past several years, the IBM Advanced Mask Facility (AMF) has focused on the fabrication of x-ray masks. Several key accomplishments have been demonstrated including fabricating masks with critical dimensions (CD) as small as 75 nm, producing line monitor masks in a pilot line mode to evaluate mask yields, and fabricating masks to make working microprocessors with the gate level defined by x-ray lithography. The experience on fabricating 1X x-ray masks is now being applied to the other NGL mask technologies. Progress on membrane and absorber materials can be applied to all the technologies, and patterning with advanced e-beam writing with chemically amplified resists utilizes learning from writing and baking on x-ray membrane masks.

At present, and for the last several decades, optical projection lithography has been the lithographic technique used in the high-volume manufacture of integrated circuits. The elementary line width of semiconductor device is now 90 nm, the extreme ultraviolet lithography (EUVL) with a wavelength in the range of 10 to 14 nm is vying to become the choice of the semiconductor industry for the so-called next generation of lithography that will enable future generations of integrated circuits to be printed with feature sizes of 45 nm and below around 2010. Plasma EUV source is regarded as the most promising source of EUV radiation, and a heated competition is underway over the world. The top priority issue for implementing EUVL is to upgrade the EUV power extensively. In the development of our Z-pinch plasma EUV source, xenon gas is used for the target. The Z-pinch plasma was driven by pulsed current with amplitude of 30 kA and pulse duration of 100 ns. Pinhole imaging, EUV spectrograph and in-band EUV energy monitor were used to characterize the EUV emission from the Z-pinch discharge plasma. In order to improve the convention efficiency (CE) from input electric energy to EUV radiation, also a solid tin rod was used as target material. The experimental analyses have demonstrated the CE was as high as 1.5%

While lithography R&D community at large has already gotten the mind set for 32nm, all eyes are on 22nm node. Current consensus is to employ computational lithography to meet wafer CD uniformity (CDU) requirement. Resolution enhancement technologies (RET) and model OPC are the two fundamental components for computational lithography. Today's full-chip CDU specifications are already pushing physical limits at extreme lithography k₁ factor. While increasingly aggressive RET either by double exposure or double patterning are enabling imaging performance, for CDU control we need ever more accurate OPC at a greater computational efficiency. In this report, we discuss the desire for wanting more robust and accurate OPC models. One important trend is to have predictive OPC models allowing accurate OPC results to be obtained much faster, shortening the qualification process for exposure tools. We investigate several key parameters constitute to accuracy achievable in computational lithography. Such as the choice of image pixel size, numbers of terms needed for transmission cross coefficients (TCC), and "safe" ambit radius for assuring accurate CD prediction. Selections of image pixel size and "safe" ambit radius together determine % utilization for 2D fast Fourier transformation (FFT) for efficient full-chip OPC computation. For IC manufacturing beyond ArF, we made initial observations and estimations on EUV computational lithography. These discussions pave the way for developing a computational lithography roadmap extends to the end of Moore's Law. This computational lithography roadmap aims to be a complement for the current ITRS roadmap on what does it take to achieve CD correction accuracy.

Optical lithography has been successfully used since the 1960s for integrated-circuit production at linewidths of several microns. At present, volume production tools operating at 193-nm wavelength deal with linewidths about 100 nm. Intel's cofounder Gordon E. Moore predicted this downscaling trend in 1965, and the leading chip manufacturers have followed "Moore's Law" during the past and plan to follow it for the coming decade with resolutions below 35 nm. According to Rayleigh's criterion, the resolution of lithography systems is directly proportional to the wavelength λ used and inversely proportional to the numerical aperture (NA) of the system. Consequently, one strategy for next-generation lithography (NGL) toward higher resolution is to decrease wavelength. Most likely, NGL optics will be based on extremely short wavelength UV light, also called soft-x-ray or EUV light, at a preferred wavelength of 13.5 nm. Other NGL options such as electron projection lithography, maskless lithography, and imprint lithography are still subjects of major research programs, but an insurmountable obstacle for these technologies is their low throughput prospects. In the case of EUVL, the very low EUV transparency of common materials implies a technology migration from transparent lenses (all-refractive optics) to mirrors (all-reflective optics). Accordingly, any EUV chip manufacturing tool (wafer scanner) will need a powerful light source and efficient reflective optical components in order to supply a sufficient number of photons for a stable resist exposure process. The main optical components of an EUVL scanner are shown schematically in Fig. 33.1. EUV light emitted from a suitable source is collected by the source optics and projected into an aperture (intermediate focus or IF), where it enters the illumination system. A uniformly illuminated field of the reticle (mask) is then imaged by the projection optics onto the resist-coated wafer. In the region of the IF an enlarged image of the source itself is created by the collector optics. High EUV reflectivity of optical surfaces, as required for such an application, can be achieved either by suitable multilayer coatings at or close to normal incidence, or by very smooth metal reflectors at grazing incidence. Several technological approaches, including plasma emission and synchrotron radiation, have been taken toward the development of a high-power EUV light source for lithography applications. Currently, the most promising EUV source types are the electrical-gas DDP and the LPP. Among other wavelengths, both types of sources emit light at around 13.5 nm into solid angles of around 2π sr or even more. For details about DPP and LPP sources, see Chapters 3 and 4, respectively. Information on some alternative sources other than DPP or LPP can be found in Chapter 6.

EUV lithography is currently the favorite and most promising candidate among the next generation lithography (NGL) technologies. Decade ago the NGL was supposed to be used for 45 nm technology node. Due to introduction of immersion 193nm lithography, double/triple patterning and further techniques, the 193 nm lithography capabilities was greatly improved, so it is expected to be used successfully depending on business decision of the end user down to 10 nm logic. Subsequent technology node will require EUV or DSA alternative technology. Manufacturing and especially process development for EUV technology requires significant number of unique processes, in several cases performed at dedicated tools. Currently several of these tools as e.g. EUV AIMS or actinic reflectometer are not available on site yet. The process development is done using external services /tools with impact on the single unit process development timeline and the uncertainty of the process performance estimation, therefore compromises in process development, caused by assumption about similarities between optical and EUV mask made in experiment planning and omitting of tests are further reasons for challenges to unit process development. Increased defect risk and uncertainty in process qualification are just two examples, which can impact mask quality / process development. The aim of this paper is to identify critical aspects of the EUV mask manufacturing with respect to defects on the mask with focus on mask cleaning and defect repair and discuss the impact of the EUV specific requirements on the experiments needed.

The concept of using Scanning Electron Microscopy and Die-to-Database techniques to rigorously inspect advanced lithography products such as X-ray Lithography, Imprint, and Stencil masks as well as other Next Generation Lithography (NGL) is compelling. Current optical capabilities reach down to 0.2μm and do so by interpolating pixilated optical data. Applications at 4x magnifications, such as Chrome on Glass or Phase Shift Photomasks mesh with this resolution of inspection and have been able to migrate down the lithography nodes hand in hand. As the demands for resolution progress, optical lithography has been increasing the requirements upon inspection systems presently available through the addition of assist features and serifs, which are difficult to directly verify. These assist features are effectively approaching 1x dimensions. A printed feature that is slightly out-of-tolerance for CD, shape, or position relative to other structures, may still yield acceptable performance. This added resolution challenge of working closer to a 1x Magnification with ever decreasing structure sizes is easily achieved with Scanning Electron Microscope technology. The Die-to-Database inspection technique utilizes the CAD image, which defines the designer's original intended structure, as the reference image. In this paper, we will introduce a revolutionary approach for utilizing the full potential of Scanning Electron Microscope images for inspection purposes. The technique incorporates an aggressive but reliable interpretation of the image data to recreate GDS data files which can then be validated against the desired GDS data for hard defects, abbreviated / missing features, and even shifts or placement errors.

The 22-nm technology node presents a real breakthrough compared to previous nodes in the way that state of the art scanner will be limited to a numerical aperture of 1.35. Thus we cannot simply apply a shrink factor from the previous node, and tradeoffs have to be found between Design Rules, Process integration and RET solutions in order to maintain the 50% density gain imposed by the Moore's law. One of the most challenging parts to enable the node is the ability to pattern Back-End Holes and Metal layers with sufficient process window. It is clearly established that early process for these layers will be performed by double patterning technique coupled with advanced OPC solutions. In this paper we propose a cross comparison between possible double patterning solutions: Pitch Splitting (PS) and Sidewall Image Transfer (SIT) and their implication on design rules and CD Uniformity. Advanced OPC solutions such as Model Based SRAF and Source Mask Optimization will also be investigated in order to ensure good process control. This work is a part of the Solid's JDP between ST, ASML and Brion in the framework of Nano2012 sponsored by the French government.

Semiconductor lithography scanners are extremely complex equipment which is used to manufacture IC(Intergrated Circuit). Moore's law, which states that the computing power per chip doubles every one and a half to two years, has consistently held for four decades. [1] The exposure system in semiconductor has been rapidly developed based on the Moore's law. Most semiconductor manufacturers have been using ASML scanner for exposure on wafers. The reticle stage of ASML scanner exists over magnet plates. The electric currents are supplied to the coil of the inside magnet，the reticle stage can move forward and backward by Fleming's left hand rule. [3] The reticle stage is synchronized with wafer stage of movement. At that time, scan speed is very fast, reticle stage scan velocity is about 2.4m/sec, in addition acceleration reaches to 9G. So the conditions are very harsh to stage. However, with current technology, we cannot manufacture the whole mass of magnet as long as long stroke of reticle stage. (approximately 2.4m) So they manufacture it on plate by attaching 600mm pieces of magnet. Over time, the magnet plates attached to the main frame are getting weak. At the end of magnet which is the weakest point can be easily cracked because it is changing of flux density in magnet plate. We analyze bonding method between magnet and plate. In addition, we tested it on a different roughness for the plate. Through the change of the material and roughness, we could improve prevent the plate from cracking. In this paper, we propose how to protect broken magnet by changing the material of adhesive and roughness of plate. As a result, we can expect to increase stability in the magnet plate on a reticle stage by more than 10%. [1] G. E. Moore, “Cramming more components onto integrated circuits,” Electron. Mag., vol. 38, no. 8, pp. 4–7, 1965.[2] Hans Butler, “Position control in lithographic equipment”, IEEE Control Systems Magazine, October 2011[3] Kenjō, Takashi, and Shigenobu Nagamori. Permanent-magnet and brushless DC motors. Vol. 18. Oxford University Press, USA, 1985. Figure 1

Historical microprocessor product trends show an increase in product frequency of 1.25x per year and a transistor count increase of 1.4x per year since the early 70's. This trend is forecast to continue over the next decade to the 0.07μm generation. To support the trend, challenges in lithography, transistor definition, interconnect system, and manufacturability must be overcome. Solutions to the lithography challenge, will require successful implementation of 157nm optical or next generation lithography (NGL). The transistor solution will require integration of sub 2.0nm gate oxides with improved gate electrode materials, improved low resistance shallow source-drain technology, advanced channel dopant engineering, and operation at or below 1.0v. Interconnect challenges will require support of 10 or more interconnect layers using low resistivity metalization and reduced epsilon dielectric. Manufacturing challenges require support of larger die sizes, integrated at higher technology complexity, while maintaining lowest possible cost.

Computational lithography has emerged as a critical driver for the continued miniaturization of semiconductor devices, enabling sub-wavelength patterning with fixed hardware (e.g., 193nm immersion lithography) through software-driven optimization of resolution enhancement techniques. However, via and metal layers face unique lithographic challenges, primarily stemming from pitch mismatches caused by differences in lithography resolution (or process window) between the two. This mismatch necessitates careful design considerations and complex process operations to mitigate issues. In most cases, such operations require concurrent modifications to adjacent layers, which not only becomes cumbersome and significantly increases labor and computational costs but also introduces new alignment and stability risks. This paper presents two specialized multi-patterning strategies leveraging negative tone development (NTD) to address these challenges. For via layers, the inherent resolution gap between holes and metal lines leads to pitch mismatches. To resolve this, we propose an NTD-based litho-litho-etch (LLE) approach: two sequential NTD exposures (without intermediate etching) transfer patterns to a hard mask, followed by a third mask to define actual via locations. By restricting each split via mask to a single direction (X or Y), source mask optimization (SMO) is simplified, enabling via pitch matching with metal layers while improving overlay accuracy and process window. For metal layers, we extend the via layer strategy: a primary mask is paired with tailored cut masks. Initial cut patterns are generated via logical operations on grid-aligned layouts, with final cuts adjusted by optical proximity correction (OPC) to account for the proximity effect. Both strategies demonstrate that, combined with NTD multipatterning, they enable precise alignment between via and metal layers (for via layout printing) and stabilize line-ends (for metal layout printing), while enhancing process windows, maximizing resolution under fixed hardware constraints, reducing mask costs, and potentially enabling further miniaturization to advance semiconductor manufacturing.

Optical lithography, currently being used for 45-nm semiconductor devices, is expected to be extended further towards the 32-nm and 22-nm node. A further increase of lens NA will not be possible but fortunately the shrink can be enabled with new resolution enhancement methods like source mask optimization (SMO) and double patterning techniques (DPT). These new applications lower the k1 dramatically and require very tight overlay control and CD control to be successful. In addition, overall cost per wafer needs to be lowered to make the production of semiconductor devices acceptable. For this ultimate era of optical lithography we have developed the next generation dual stage NXT:1950i immersion platform. This system delivers wafer throughput of 175 wafers per hour together with an overlay of 2.5nm. Several extensions are offered enabling 200 wafers per hour and improved imaging and on product overlay. The high productivity is achieved using a dual wafer stage with planar motor that enables a high acceleration and high scan speed. With the dual stage concept wafer metrology is performed in parallel with the wafer exposure. The free moving planar stage has reduced overhead during chuck exchange which also improves litho tool productivity. In general, overlay contributors are coming from the lithography system, the mask and the processing. Main contributors for the scanner system are thermal wafer and stage control, lens aberration control, stage positioning and alignment. The back-bone of the NXT:1950i enhanced overlay performance is the novel short beam fixed length encoder grid-plate positioning system. By eliminating the variable length interferometer system used in the previous generation scanners the sensitivity to thermal and flow disturbances are largely reduced. The alignment accuracy and the alignment sensitivity for process layers are improved with the SMASH alignment sensor. A high number of alignment marker pairs can be used without throughput loss, and furthermore the GridMapper functionality which is using the inter-die and intra-die scanner capability can reduce overlay errors coming from mask and process without productivity impact. In this paper we will present the main design features and discuss the system performance of the NXT:1950i system, focusing on the improvements made in overlay and productivity. We will show data on imaging, overlay, focus and productivity supporting the 3X-nm node and we will discuss next improvement steps towards the 2X-nm node.

The lithographic performance of a photomask is sensitive to shape uncertainty caused by manufacturing and measurement errors. This work proposes incorporating the photomask shape uncertainty in computational lithography such as inverse lithography. The shape uncertainty of the photomask is quantitatively modeled as a random field in a level-set method framework. With this, the shape uncertainty can be characterized by several parameters, making it computationally tractable to be incorporated in inverse lithography technique (ILT). Simulations are conducted to show the effectiveness of using this method to represent various kinds of shape variations. It is also demonstrated that incorporating the shape variation in ILT can reduce the mask error enhancement factor (MEEF) values of the optimized patterns, and improve the robustness of imaging performance against mask shape fluctuation.

In DSAL, a mask contains the image of guide patterns (GPs) not the image of final contacts or vias. Thus, a wafer receives GP patterns after optical lithography is applied to the mask. It then goes through a DSA process, and contacts are finally patterned. Mask design for DSAL, which is, in fact, the opposite of the above-mentioned process, consists of two key steps, inverse DSA and inverse lithography. In inverse DSA, GPs are progressively refined until they are estimated to produce contacts that are close to target ones as much as possible. For this purpose, GP is defined as a function of a few geometry parameters, and the sensitivity of contact to each parameter is repeatedly calculated to guide how much GP should be refined. In inverse lithography, mask is progressively refined until it is believed to produce target GPs. Mask is defined by a grid of pixel values (rather than by a set of edges) and their gradient guides the direction that the mask should be refined. There are typically too many pixels for gradient calculation; the method to approximate calculation is described in this chapter. Inverse DSA and inverse lithography are extended to handle process variations. The basic inverse lithography is modified so that the resulting mask becomes less sensitive to lithography variations; basic inverse DSA is modified so that it provides the way this sensitivity can be checked.