Locality-Aware Process Scheduling for Embedded MPSoCs

Increasing the life span and efficiency of Multiprocessor System on Chip (MPSoC) by reducing power and energy utilization has become a critical chip design challenge for multiprocessor systems. With the advancement of technology, the performance management of central processing unit (CPU) is changing. Power densities and thermal effects are quickly increasing in multi-core embedded technologies due to shrinking of chip size. When energy consumption reaches a threshold that creates a delay in complementary metal oxide semiconductor (CMOS) circuits and reduces the speed by 10%–15% because excessive on-chip temperature shortens the chip’s life cycle. In this paper, we address the scheduling & energy utilization problem by introducing and evaluating an optimal energy-aware earliest deadline first scheduling (EA-EDF) based technique for multiprocessor environments with task migration that enhances the performance and efficiency in multiprocessor system-on-chip while lowering energy and power consumption. The selection of core and migration of tasks prevents the system from reaching its maximum energy utilization while effectively using the dynamic power management (DPM) policy. Increase in the execution of tasks the temperature and utilization factor on-chip increases that dissipate more power. The proposed approach migrates such tasks to the core that produces less heat and consumes less power by distributing the load on other cores to lower the temperature and optimizes the duration of idle and sleep times across multiple CPUs. The performance of the EA-EDF algorithm was evaluated by an extensive set of experiments, where excellent results were reported when compared to other current techniques, the efficacy of the proposed methodology reduces the power and energy consumption by 4.3%–4.7% on a utilization of 6%, 36% & 46% at 520 & 624 MHz operating frequency when particularly in comparison to other energy-aware methods for MPSoCs. Tasks are running and accurately scheduled to make an energy-efficient processor by controlling and managing the thermal effects on-chip and optimizing the energy consumption of MPSoCs.

The performances of System on Chip (SoC) and the Field Programmable Gate Array (FPGA) particularly, are increasing continually. Due to the growing complexity of modern embedded control systems, the need of more performance digital devices is evident. Recent FPGA technology makes it possible to include processor cores into the FPGA chip, which ensures more flexibility for digital controllers. Indeed, greater functionality of hardware and system software, Real-Time (RT) platforms and distributed subsystems are demanded. In this chapter, a design concept of FPGA based controller with Hardware/Software (Hw/Sw) codesign is proposed. It is applied for electrical machine drives. There are discussed different MultiProcessor SoC (MPSoC) architectures with Hw peripherals for the implementation on FPGA-based embedded processor cores. Hw accelerators are considered in the design to enhance the controller speed performance and reduce power consumption. Test and validation of this control system are performed on a RT motor emulator implemented on the same FPGA. Experimental results, carried on a real prototyping platform, are given in order to analyze the performance and efficiency of discussed architecture designs helping to support hard RT constraints.Request access from your librarian to read this chapter's full text.

Multiprocessor System on Chip (MPSoC) technology can present an interesting solution to reduce the computational time of complex applications. Execute the H.264/AVC encoder on MPSoC architecture, is becoming an interesting point of research that can mitigate its algorithmic complexity and to resolve the real time constraints. In this paper, we present an efficient MPSoC architecture for the intra prediction process which is an important module of the H.264/AVC video encoder, using Data Level Parallelism (DLP) partitioning. This architecture is tested on an open platform for MPSoC architectures virtual designing (SoCLiB), and validated on FPGA technology. Experimental results show a gain of 74% in term of encoding speed when using four processors for coding a High Definition Video sequence (HDV) compared to uni-processor architecture.

Multi-Processor System-On-Chip (MPSoC) can provide the performance levels required by high-end embedded applications. However, they do so at the price of an increasing power density, which may lead to thermal runaway if coupled with low-cost packaging and cooling. Hence, mechanisms to efficiently evaluate the effectiveness of advanced thermal-aware operating-system (OS) strategies (e.g. task migration) onto the available MPSoC hardware are needed. In this paper, we propose a new MPSoC OS emulation framework that enables the study of thermal management strategies at the architectural- and OS-levels with the help of a standard FPGA. This framework includes the hardware and software components needed to accurately model complex MPSoCs architectures, and to test the effects of run-time thermal management strategies at the OS/middleware level with real-life inputs. Our results show that migration overhead is negligible w.r.t. temperature timings, enabling the development of thermal-aware migration strategies. Moreover, the effectiveness of the monitoring and feedback mechanism provides an emulation performance only ten times slower than real time.

Traditional development of reliable device drivers for multiprocessor system on chip (MPSoC) is a complex and demanding process, as it requires interdisciplinary knowledge in the fields of hardware and software. This problem can be alleviated by an advanced driver generation environment. We have achieved this by systematically synthesizing drivers from a device features model and specifications of hardware and in-kernel interfaces, thereby lessening the impact of human error on driver reliability and reducing the development costs. We present the methodology called Me3D and confirm the feasibility of the driver generation environment by manually converting sources of information captured in different formalisms to a Multimedia Card Interface (MCI) driver for a real MPSoC under a lightweight operating system (OS).

The design of a Multiprocessor System-on-Chip (MPSoC) is a complex task, including steps as application development, platform configuration, code generation, task mapping onto the platform and debugging. An integrated environment covering most of these steps is a gap in the literature. The present work first details an MPSoC architecture, which supports the execution of distributed applications, including an operating system enabling multitask execution at each processing element. The MPSoC is heterogeneous, due to the support to different processor architectures. Then, a framework able to cover the design steps previously mentioned is presented. The framework enables the design space exploration for applications to be executed in the MPSoC, varying for example the number and type of processors, the memory size, the task mapping. Results demonstrate the correct operation for different MPSoC configurations, generated from the proposed framework. Such open-source framework enables the research community to investigate new subjects related to MPSoC and Network on Chip (NoC) design, as well as evaluate distributed applications in a multiprocessor environment.

With technology scaling, Multiprocessor System on Chip (MPSoC) which consist of multiple processors connected via a Network on Chip (NoC) have become prevalent. Applications are mapped to MPSoC's by representing it in the form of a task graph. Task scheduling involves mapping task to processor cores so as to meet the deadline. For a given deadline, slack at each node is defined by the amount of time by which a task execution can be delayed without missing the deadline. With increase in the number of cores and high application parallelism, NoC is becoming a bottleneck due to the presence of large number of concurrent communications. Increasing network resources (links and routers) reduces the communication time but the area and power goes up. In this paper we present an application aware heuristic to synthesize a minimal network connecting a set of cores in an MPSoC in the presence of hard deadlines. Our approach is based on modeling communication between a pair of processors as tasks known as “Comtasks”. The network is generated by “scheduling” these comtasks onto a set of routers so as to obtain a network with minimum area which fills up the available slack. Moreover, we also identify the set of overlapping comtasks and generate a minimal network to allow the maximum set of overlapping comtasks to execute concurrently. We compared our approach with a greedy network generation heuristic and the results show 80% benefit in the router area.

Reconfigurable technologies are getting popular as an instrument not only for verification and prototyping but also for commercial implementation of Multi-Processor System-on-Chip (MPSoC) architectures. These systems, in particular Network-on-Chip (NoC) based ones, have emerged as a design strategy to cope with increased requirements and complexity of modern applications. However, the increasing heterogeneity, coupled with possibility of reconfiguration, makes security become one of major concerns in MPSoC design. In this work, we show a solution for FPGA based designs against one of the most widespread types of attacks - code injection. Our response to tackle this challenge is given in form of Stack Protection Unit (SPU) embedded into processing cores. MicroBlaze soft-core processor serves as a case study for verification of the proposed solution in FPGA technology.

Sharing of functional units inside a processor by two applications can lead to to information leaks and micro-architectural side-channel attacks. Meanwhile, processors now commonly come with hardware performance counters which can count a variety of micro-architectural events, ranging from cache behavior to floating point unit usage. In this paper we propose that the hardware performance counters can be leveraged by the operating system's scheduler to predict the upcoming program phases of the applications running on the system. By detecting and predicting program phases, the scheduler can make sure that programs in the same program phase, i.e. using same type of functional unit, are not scheduled on the same processor core, thus helping to mitigate potential side-channel attacks.

The Safe and Precise Landing Integrated Capabilities Evolution (SPLICE) project continues NASA's technology development for Precision Landing and Hazard Avoidance (PL&HA). The High-Performance Space Computing (HPSC) project manages a contract to build a multi core processor that is intended to be NASA's computing platform for future human and robotic spaceflight missions. This paper describes the flight computer for the PL&HA payload that will be used in SPLICE flight testing onboard suborbital rockets. This computer is being designed as a surrogate architecture for the HPSC chip, using a Xilinx Multi-Processor System on a Chip (MPSoC). Field testing with the surrogate architecture facilitates cross-agency experience with the HPSC and positions projects for future technology infusion opportunities. The MPSoC is hosted on a custom baseboard and interfaced to a second custom board that provides the sensor and vehicle interfaces. Early design trades for the SPLICE surrogate implementation are described. Preliminary performance testing on the surrogate platform using an optical navigation algorithm developed for the Orion vehicle is described, and shows 2.5 times execution speedup resulting from minimal modifications to the original code. In general, High Performance Computing/Embedded Computing (HPC/HPEC) required to address computational challenges in a wide range of NASA missions has consistently had challenges in implementation due to the diversity in the disciplines required to develop a solution. Typically, algorithm designers with expertise in the physics of the problem, and numeric approaches to solving the relations that model the physics, do not have expertise in processing architectures. There are strong dependencies between the overall performance of the system and the choices made in the modeling of the physics, the numerical approaches to solutions for the physical relations, and how these operations are mapped to computational resources in an architecture. To address this concern, a Model-Based Systems Engineering (MBSE) based concept for conducting multi-disciplinary co-design of the Guidance, Navigation, and Control (GN&C) algorithms, processing hardware configuration, and system software is introduced.

As application complexity continues to increase, multiprocessor systems-on-chip (MPSoC) with tens to hundreds of processing cores are becoming the norm. While computational cores have become faster with each successive technology generation, communication between them has become a bottleneck that limits overall chip performance. On-chip optical interconnects can overcome this bottleneck by replacing electrical wires with optical waveguides. In this paper we propose an optical ring bus (ORB) based on-chip communication architecture for next generation MPSoCs. ORB uses an optical ring waveguide to replace global pipelined electrical interconnects while preserving the interface with today's bus protocol standards such as AMBA AXI. We present experiments to show how ORB has the potential to provide superior performance (more than 2times) and significantly lower power consumption (a reduction of more than 10times) compared to traditionally used pipelined, all-electrical bus-based communication architectures, for 65-22 nm technology nodes.

This article distinguishes the difference between dynamic operating system and static operating system from the design goal, and discusses the resulting difference in the technology used in system implementation. With this as the theoretical basis, according to the ISO17356 OS specification, using hardware abstraction layer design ideas, a simple and efficient static real-time operating system is implemented on the ARM platform. This paper adopts the idea of separating mechanism and strategy, and uses internal resources as a mechanism to implement different scheduling strategies; a task scheduling algorithm based on priority grouping is proposed, which achieves good performance in time and space.

This paper presents principles and tools to facilitate multi-processor system on chips (MPSoCs) design and modeling, and to speed up cycle accurate SystemC simulation. We describe an effective way to build an hardware architecture virtual prototype, using a library of SystemC simulation models based on communicating synchronous finite state machines. This modeling approach supports a fully static scheduling strategy, based on the analysis of the combinational dependency graph. Our static scheduling algorithm has been implemented in the SystemCASS simulator, and provides speed-up of one order of magnitude versus the standard event-driven SystemC simulation engine. The modeling approach proposed in this paper has been adopted by the SoCLIB French National Project, that is an open modeling and simulation platform for multi-processors system on chips.

With increasing core counts ushering in power-constrained 3-D multiprocessor system-on-chips (MPSoCs), optimizing communication power dissipated by the 3-D network-on-chip (NoC) fabric is critical. At the same time, with increased power densities in 3-D ICs, problems of IR drops in the power delivery network (PDN) as well as thermal hot spots on the 3-D die are becoming very severe. Even though the PDN and NoC design goals are nonoverlapping, both the optimizations are interdependent. Unfortunately, designers today seldom consider the design of the PDN, while designing NoCs. Moreover, for each new configuration of computation core and communication mapping on an MPSoC, the corresponding intercore communication patterns, 3-D on-chip thermal profile, as well as IR-drop distribution in the PDN can vary significantly. Based on this observation, we propose a novel design-time system-level application-specific cosynthesis framework that intelligently maps computation and communication resources on a die, for a given workload. The goal is to minimize the NoC power as well as chip-cooling power and optimize the 3-D PDN architecture; while meeting performance goals and satisfying thermal constraints, for a microfluidic cooling-based application-specific 3-D MPSoC. Our experimental results indicate that the proposed 3-D NoC-PDN cosynthesis framework is not only able to meet PDN design goals unlike prior 3-D NoC synthesis approaches, but also provides better overall optimality with the solution quality improvement of up to 35.4% over a probabilistic metaheuristic-based cooptimization approach proposed in prior work.

Real-time multimedia applications are increasingly being mapped onto MPSoC (multiprocessor system-on-chip) platforms containing hardware--software IPs (intellectual property), along with a library of common scheduling policies such as EDF, RM. The choice of a scheduling policy for each IP is a key decision that greatly affects the design's ability to meet real-time constraints, and also directly affects the energy consumed by the design. We present a cosynthesis framework for design space exploration that considers heterogeneous scheduling while mapping multimedia applications onto such MPSoCs. In our approach, we select a suitable scheduling policy for each IP such that system energy is minimized—our framework also includes energy-reduction techniques utilizing dynamic power management. Experimental results on a realistic multimode multimedia terminal application demonstrate that our approach enables us to select design points with up to 60.5% reduced energy for a given area constraint, while meeting all real-time requirements. More importantly, our approach generates a tradeoff space between energy and cost allowing designers to comparatively evaluate multiple system level mappings.