Logic circuit elements using single-electron tunnellingtransistors

This work presents the response of SETs silicon, quartz, and sapphire substrates to applied potential on a second gate SET gate. The SETs used are fabricated using electron beam (e-beam) lithography and the Dolan bridge technique. Measurements are performed at temperature range of 0.3 4.2 K. We observed a breakdown in compensation (seen as CBOs with varied period) in devices on Si substrates but not in devices on the insulating wide bandgap substrates, quartz and sapphire, which have no mobile charges. In these substrates it is possible to achieve an almost ideal charge cancellation over a large range of gate voltages (tens of volts).

The noise in current biased aluminium single electron tunneling (SET) transistors has been investigated in the frequency range of 5 mHz<f<30 Hz. A refined high frequency (HF) shielding including resistive coaxial lines, that prevents spurious electromagnetic radiation and especially high energy photons emitted by the 4.2 K environment from reaching the sample, allows us to study a given background charge configuration for many hours below ≈100 mK. The noise at relatively high frequencies originates from internal (presumably thermal equilibrium) charge fluctuations. For f⩾10 Hz, we find the same input charge noise, typically QN=5×10−4 e/Hz1/2 at 10 Hz, with and without the HF shielding. At lower frequencies, the noise is due to charge trapping, and the voltage noise pattern superimposed on the V(Vg) curve (voltage across transistor versus gate voltage) strongly depends on the background charge configuration resulting from the cooling sequence and eventual radio frequency (rf) irradiation. The measured noise spectra which show both 1/f and 1/f1/2 dependencies and saturation for f<100 mHz can be fitted by two-level fluctuators with Debye–Lorentzian spectra and relaxation times of order seconds. In some cases, the positive and negative slopes of the V(Vg) curve have different overlaid noise patterns. For fixed bias on both slopes, we measure the same noise spectrum, and believe that the asymmetric noise is due to dynamic charge trapping near or inside one of the junctions induced when ramping the junction voltage. Dynamic trapping may limit the high frequency applications of the SET transistor. Also reported on are the effects of rf irradiation and the dependence of the SET transistor noise on bias voltage.

This paper presents a neuron structure that resembles the basic McCulloch and Pitts model and is suitable for an implementation with single-electron tunneling (SET) transistors only or as a SET/FET hybrid. It combines a basic neuron with nine binary-programmable synapses and a programmable bias term. With these synaptic inputs the neuron is suitable for building a processing array like the cellular neural network (CNN) for processing black and white (BAY) images. The binary programming scheme is fast and robust, and thus it can be applied to architectures based on nanodevices. The cell structure and operation principles are described and illustrated by simulation results

We experimentally demonstrated single-electron operations of an AND/NAND logic circuit based on a self-organized GaAs quantum-dot (QD) network fabricated by applying a selective-area metalorganic vapor-phase epitaxy technique. Single-electron logic operations using four cooperating single-electron tunneling (SET) transistors has been tested. This logic circuit has an architecture based on a binary decision diagram (BDD) using a Coulomb blockade (CB) in GaAs QDs, which is a representation of digital logic functions using directed graphs. BDD node devices consisting of two SET transistors achieved a two-way path switching operation in single-electron mode due to the CB effects which appeared complementarily in the two SET transistors at 1.9 K. We also demonstrated an AND/NAND operation in a logic circuit by integrating two BDD nodes.

Assuming the absence of 1/f noise, we have calculated the charge sensitivity (CS) of a capacitive-coupled double-junction single electron tunneling transistor (SETT) with a superconducting grain, operating at low temperature and low bias voltage such that the tunneling current is dominated by the Andreev process. In this case the effect of co-tunneling is suppressed without using the complicated fabrication method. We have used a realistic sample to demonstrate the procedure of optimizing the CS of a SETT with respect to relevant physical parameters and structure parameters. With the presently available fabrication technology, our theoretical analysis can serve as a guide for increasing the CS of a SETT beyond 10−6 e/√Hz.

We theoretically investigate effects of quantum fluctuation between an even and an odd charge state on the transport properties of a normal-superconducting-normal--single-electron tunneling transistor. The charge fluctuation is discussed beyond the orthodox theory. We find that the charging energy renormalization enhances the parity effect: The Coulomb blockade regime for the odd state is reduced and that for the even state is widened. We show that the renormalization factor can be obtained experimentally and that the renormalization effect is weakened by applied bias voltage.

Two-dimensional (2D) semiconductors have emerged as promising candidates for enabling complementary metal-oxide-semiconductor (CMOS) technology in post-silicon electronics. However, a significant performance gap between 2D p-type and n-type transistors hampers their immediate industrial application. In this Comment, we discuss recent advances in high-performance 2D p-type transistors, outline a roadmap for their potential development, and propose benchmark performance metrics to guide future progress. The performance of p-type transistors based on 2D semiconductors has not yet reached the level required for the realization of competitive complementary metal-oxide-semiconductor (CMOS) circuits. In this Comment, the authors discuss the recent developments, current challenges, and future outlook of 2D p-type transistors.

Study of random telegraph signals in a GaAs/AlxGa1 − xAs single electron transistor

Kilohertz organic complementary inverters driven by surface-grafting conducting polypyrrole electrodes

Nanofabrication by electron beam lithography and its applications: A review

Quantum confinement in 3-D device structure together with the newly employed materials like silicon-germanium (SiGe) in advanced technologies (e.g., FinFET, nanowire, nanosheets, etc.) makes transistors seriously suffer from localized self-heating effects in which generated heat within the transistor’s channel is trapped inside. This is mainly due to the much lower channel and surrounding material thermal conductivity and hence lower ability for heat dissipation along with the firm isolation needed for better gate control. Self-heating effects strongly accelerate transistor aging and all the underlying defect generation mechanisms leading to serious reliability problems during the early life of chips. The key challenge in transistor self-heating when it comes to semiconductor testing is the profound difficulty in measuring self-heating directly as generated heat is trapped inside the transistor. Failing in capturing self-heating phenomenon during IC testing would later lead to chips malfunctions at run-time and hence early life failures because of reliability degradations and failure mechanisms will be unexpectedly accelerated akin to excessive internal temperatures. In this paper, we investigate the impact of self-heating effects on n-type and p-type FinFET transistors calibrated with Intel 14 nm measurement data using mature Technology CAD (TCAD) simulations. Then, the industry standard compact model for FinFET technologies (BSIM-CMG) is carefully calibrated to accurately model and reproduce all measurements. This enables circuit’s designers, for the first time, to accurately investigate how emerging self-heating effects in transistors impacts the performance and power of large circuits. This opens new doors for developing novel Design-for-Testing methods that effectively reveal self-heating effects and increase the yield of chips.

The asymmetry of the current-voltage characteristic of a single-electron tunnelling transistor causes a current rectification when applying a low-frequency voltage signal. The polarity of the direct current depends on the voltage applied to a gate electrode. The characteristic change in current polarity with increasing gate voltage can be used to detect a difference in the low frequency excitation, and also the high frequency excitation of the two electron reservoirs coupled to the electronic island.

There is ample evidence that organic field-effect transistors have reached a stage where they can be industrialized, analogous to standard metal oxide semiconductor (MOS) transistors. Monocrystalline silicon technology is largely based on complementary MOS (CMOS) structures that use both n-type and p-type transistor channels. This complementary technology has enabled the construction of digital circuits, which operate with a high robustness, low power dissipation and a good noise margin. For the design of efficient organic integrated circuits, there is an urgent need for complementary technology, where both n-type and p-type transistor operation is realized in a single layer, while maintaining the attractiveness of easy solution processing. We demonstrate, by using solution-processed field-effect transistors, that hole transport and electron transport are both generic properties of organic semiconductors. This ambipolar transport is observed in polymers based on interpenetrating networks as well as in narrow bandgap organic semiconductors. We combine the organic ambipolar transistors into functional CMOS-like inverters.

We present an 8b general-purpose microprocessor realized in a hybrid oxide-organic complementary thin-film technology. The n-type transistors are based on a solution-processed n-type metal-oxide semiconductor, and the p-type transistors use an organic semiconductor. As compared to previous work utilizing unipolar logic gates [1], the higher mobility n-type semiconductor and the use of complementary logic allow for a >50x speed improvement. It also adds robustness to the design, which allowed for a more complex and complete standard cell library. The microprocessor consists of two parts, a processor core chip and an instruction generator. The instructions are stored in a Write-Once-Read-Many (WORM) memory formatted by a post-fabrication inkjet printing step, called Print-Programmable Read-Only Memory (P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ROM). The entire processing was performed at temperatures compatible with plastic foil substrates, i.e., at or below 250°C [2].

This paper describes a low-distortion Class E power amplifier which is suitable for integrated circuit implementation. Both N-type and P-type transistors are employed to achieve a balanced circuit operation thereby reducing the significant distortion of the conventional Class E power amplifier. The power amplifier operates at 1.8 GHz and is simulated with a 0.6-/spl mu/m CMOS process at a supply voltage of 2.5 V.