Long-term tool elimination planning for a wafer fab

In today's competitive semiconductor business environment, wafer manufacturers are facing continuous pressure to accurately predict cycle time and tool utilization, gauge the impact of changes in capacity available, assess the impact of changes in product mix and quantity, and determine action plans to improve operational performance. Discrete event simulation (DES) is a widely used approach to perform such an analysis. However, DES has some inherent shortcomings for these planning tasks. Analytical models, like queueing networks, have much shorter response times and additional advantages compared to DES. But due to the complexity of semiconductor manufacturing systems (SMS) queueing models were not able to model all the peculiarities of those. This paper provides an overview of the main features of the IBM Enterprise Production planning and Optimization System (EPOS), a queueing network based system, which closes this gap. EPOS has been in use in the 300 mm fabrication of IBM in Fishkill for more than 2 years and has turned out to be an invaluable tool to analyze the trade-offs of cycle time and capacity within this complex environment.

In today?s competitive semiconductor business environment, wafer manufacturers are facing continuous pressure to accurately predict cycle time and tool utilization, gauge the impact of changes in capacity available, assess the impact of changes in product mix and quantity, and determine action plans to improve operational performance. Discrete event simulation (DES) is a widely used approach to perform such an analysis. However, DES has some inherent shortcomings for these planning tasks. Analytical models, like queueing networks, have much shorter response times and additional advantages compared to DES. But due to the complexity of semiconductor manufacturing systems (SMS) queueing models were not able to model all the peculiarities of those. This paper provides an overview of the main features of the IBM Enterprise Production planning and Optimization System (EPOS), a queueing network based system, which closes this gap. EPOS has been in use in the 300 mm fabrication of IBM in Fishkill for more than 2 years and has turned out to be an invaluable tool to analyze the trade-offs of cycle time and capacity within this complex environment.

While flexibility improvement is among the top concerns of manufacturing managers, managers are advised to choose the dimensions of flexibility they want in their plants. This study investigates the strategic choice of aligning flexibility development with the external environment that manufacturing managers face. Considering the nature of the high-technology industry in Taiwan, we measure environmental uncertainty based on the dimensions of customer demand, supply, competitors and product technology. Empirical data were collected from manufacturing firms in Taiwan. We then applied path analysis to examine the effect of aligning three types of flexibility: product mix, new product and volume with specific dimensions of environmental uncertainty. The results indicate that the matching of manufacturing flexibility with environmental uncertainty is necessary to ensure profit and sales performance. When faced with certain environmental stimuli, management should choose to emphasize and develop particular manufacturing flexibility.

With companies continually striving to reduce cycle time on the heels of significant gains, many are finding that further substantial improvement is difficult to achieve. John Carter will discuss factors influencing the limits to cycle time reduction and how to overcome those obstacles to gain further advantages. He discusses how to gain competitive advantage by coupling product development and product portfolio strategy. The result is a review of the trade off between the product portfolio and time to market. Benchmarks and best practices will be presented that can help you optimize your product mix in order to minimize cycle time and maximize profit potential.

At early stages of front end loading (FEL) of steam-based thermal recovery projects, oil companies make critical strategic decisions with limited understanding on how reservoir complexity, uncertainty and risk could affect recovery and economic performance. A solution is to measure front end loading (FEL) and improving it to meet a minimum level of project definition for sound strategic decisions. This paper presents a method to measure FEL by combining complexity and definition rating indices that account for a) reservoir structural, stratigraphic, rock, fluid, energy, static and dynamic complexity and b) definition rating indices and completeness of wells and surface infrastructure. Causal maps guide the assessment of complexity, uncertainty and risk in CAPEX, OPEX and cycle time of typical projects. Sixty-eight factors in eight matrices provide complexity indices and twelve additional factors account for completeness and definition indices for wells and reservoir under static and dynamic conditions. Five hypothetical examples using actual field data from analogs, illustrate how the method works. A causal map describes cause and effect relationships of uncertainty and risk for typical ranges of CAPEX, OPEX and project cycle times which translate into probability of success (POS). Finally, general strategies provide guidelines to reduce uncertainties and mitigate risks. By measuring and improving FEL companies increase the probability of success by mitigating risks such as higher operational expenditures (OPEX) to meet demand of energy, higher capital expenditures (CAPEX) for oversized processing facilities, and deferred production due to failures caused by extreme operating conditions imposed by high temperature, high pressure and corrosive contaminants. This method confirms the benefits of measuring the level of definition of a project, which is a best practice used in aerospace, nuclear, chemical, and other complex industries. It also improves the level of inter-disciplinary communication typical of reservoir-well-surface systems in steam-based EOR projects.

Table lookups are one of the most frequently-used operations in symmetric key ciphers. Particularly in the newer algorithms such as the advanced encryption standard (AES), we frequently find that the greatest fraction of the execution time is spent during table lookups, varying between 34% and 72% for the five representative ciphers we consider: AES, Blowfish, Twofish, MARS, and RC4. In order to accelerate and parallelize these table lookups, we describe a new parallel table lookup (ptlu) instruction. Our synthesis results indicate that such an instruction can be added to a basic RISC processor with no cycle time impact. We compare the performance of the ptlu instruction with the speedups available through more conventional architectural techniques such as multiple-issue execution. We find that the performance benefits of using the ptlu instruction can be far higher than increasing the number of instructions executed per cycle in superscalar or VLIW processors.

Over the past few years, Wafer Level Chip Size Packages (WLCSPs) have gained widespread adoption, due to their ability to deliver higher performance at lower or equivalent costs when compared to competing packages. WLCSPs have been an excellent fit for the handheld/portable industry, where the strong push for cost-reduction and miniaturization, coupled with relatively relaxed reliability requirements, have motivated true chip-sized packages requiring no underfill or overmold. Reliability performance initially limited the application of WLCSPs to small die sizes (<2.5mm), low pin counts (<25) and mature silicon technology nodes. Also, to date, a majority of WLCSPs have been built at a 0.5mm bump pitch, although there is increasing growth in the use of WLCSPs at 0.4mm pitch. These factors have allowed WLCSP packaging to flourish in the mixed signal and analog market space. With the maturity in this market segment, the WLCSP is beginning to transition from an advanced package to a commodity package and is subject to the price-pressure that accompanies this transition. More recently, the semiconductor industry has seen advances in WLCSP technology which have enabled the qualification envelope to be expanded to products with pin counts > 120. These advances have facilitated the use of WLCSPs for other component types such as RF, high speed, broadband and memory, many of which require advanced silicon technology nodes as well. Consequently, WLCSP is expanding to markets and applications previously supported by QFN and flip chip CSP. This expansion puts additional price and cycle time pressure on WLCSP manufacturing. The cycle time pressure is further enhanced by the changing business models and supply chain strategies adopted by companies in the new economic environment. To meet these growing market demands, WLCSP providers are faced with the challenges of providing faster cycle times and higher capacity without significant increases in capital expenditure. The above factors have driven the need for new WLCSP technologies that utilize fewer process steps compared to common WLCSP product offerings, while maintaining the robustness necessary for meeting quality and reliability requirements. Amkor is developing multiple WLCSP technology platforms to cater to the cost and performance requirements of the diverse application space. This paper will provide examples that significantly reduce overall package cost by removing photolithography layers. Each photomask layer removed saves in material costs, capital depreciation costs, overhead, and process cycle time. Materials, package size, and internal qualification vehicles are carefully chosen as part of Amkor's product introduction for the proposed process flows. This paper will examine material options, i.e., polymers and solder alloys, for these new structures and will also examine the effects of die sizes and I/O counts on product reliability. Detailed analyses of the failure modes produced during reliability testing will be coupled with mechanical simulations to enhance understanding of the failure mechanisms and to further strategies for improving product reliability.

Predicting the mean cycle time as a function of throughput and product mix is helpful in making the production planning for cluster tools. To predict the mean cycle time, detailed simulation models may be used. However, detailed models require much development time, and it may not be possible to estimate all model parameters. Instead of a detailed simulation model, we propose to use a so-called aggregate model to predict the mean cycle time as a function of throughput and product mix. The aggregate model is a lumped-parameter representation of the queueing system. We estimate the parameters of the aggregate model from arrival and departure data using the Effective Process Time (EPT) concept. The proposed method is illustrated for a simulation test case and a Crolles2 cluster tool workstation. The method accurately predicts the mean cycle time in a region around the workstations' operational product mix.

Optimization Practice Problems

We present a FAB Simulator (FS) and Capacity Planner (CP) that permits the operational planner to introduce new product into an existing production mix with confidence as to the customer delivery dates and FAB Capacity This paper describes the implementation of these two dynamic tools in a semiconductor FAB in Arizona. These tools assist the operational planner with the planning of the daily production mix. This FAB produces 100's of different bipolar devices using 36 process flows. The key to success in calculating present and future production goals is real time operational level tracking. Real time tracked data includes data gathered from the Manufacturing Execution System (MES) for each product's work-in-process (WIP), process flow routing, and data gathered from the equipment utilization and emergency maintenance databases. This key information is fed through a GUI linked to the CP which in turn controls the stochastic dynamic simulation model of the FS. These links provide the operational planner with dynamic production data in real time and simulated time for decision-making. The CP and FS are running in parallel and are linked directly with the FAB's MES maintaining current production data.

Data storage tiers are increasing in size to support the demands for high capacity and performance, and so the tiers with a capacity of hundreds of TB or even PB are becoming more prevalent. The design of a storage tier of this scale is a complex task involving many competing criteria such as capital expenditure (CapEx) and operational expenditure (OpEx). In this paper we present an Operations Research (OR) approach for the optimal design of storage tiers -- by taking various considerations from the system components and their interconnections -- so as to ultimately scale out to a much larger storage tier. By combining well-known Integer Programming in an innovative way we can automatically design storage tiers with capacities of hundreds of TB in reasonable time. Additionally, we demonstrate our method using a real-world case study involving the design of a disk-based archival storage tier.

This paper addresses the operational issues of transport strategies in tool and vehicle dispatching integration (TVDI) architecture in a fully automated manufacturing wafer fab. At present, there are three transport strategies involved in vehicle dispatching, namely, avoid blocking, avoid starvation, and accelerate batch preparation. These strategies were developed to obviate production obstacles and to avoid capacity loss. Consequently, there are five levels in the decision-making process of TVDI, namely, dispatching request, conditions checking, candidate selection, dispatching rules, and result execution. Specifically, candidate selection was classified into five categories: FOUP-selects-tool (FST), FOUP-selects-stocker (FSS), tool-selects-FOUP (TSF), FOUP-selects-vehicle (FSV), and vehicle-selects-FOUP (VSF). The proposed transport strategies were implemented in VSF, and a simulation model abstracted from a wafer fab in Taiwan was used to evaluate the performance. The results show that the differences in the proposed strategies compared with ignoring the issues are statistically significant, and the performances of the wafer output, cycle time and waiting time can be improved.

The development of a parking plan for a relocated airport requires detailed documentation of parking demand forecasts, capacity assessment, revenues, and capital expenditures. These tasks are heavily dependent on characteristics of the access trip to the airport. Parking capacity requirements are estimated via passenger classification and discrete choice modeling at the existing airport. Both are conducted via passenger and parking survey studies specifically designed for this purpose. The resulting models are then used to forecast the short-term and long-term parking supply for the relocated airport by proper adjustment of the attribute values. The method is applied to the new Athens International Airport.

Semiconductor wafer manufacturing is among the most complex manufacturing processes, and hence a capital-intensive endeavor. The most common non cost-related performance measures for a semiconductor manufacturing facility are machine utilization, production yield, throughput, and last but not least cycle time. We define cycle time as the time a lot of wafers needs to travel through the semiconductor wafer manufacturing process. The overall cycle time of a lot of wafers is the sum of the total processing times of a wafer, waiting times for all resources (such as operators, machines, tools, transportation system) needed for each processing step to become available, times elapsed during measurement and quality inspections, and the time the lot has spent in transportation.

The sludge-water mixture in anaerobic reactors with confined sludge, such as the upflow anaerobic sludge blanket (UASB) with anaerobic sludge confined in a sludge bed and the internal reflux packed-bed anaerobic reactor with anaerobic sludge attached to a filler, can be mixed according to the designed hydraulic dynamic process. In this study, sludge-water mixing models of an UASB and an internal reflux packed-bed anaerobic reactor were established and validated using test models reported in the literature. The sludge-water mixing in the UASB consists of an advective diffusion unit and a water complete mixing output unit connected in series. The sludge-water mixing and reaction of the internal reflux packed-bed anaerobic reactor achieved that of a continuous stirred tank reactor (CSTR) in large-scale reflux transport mode with cycle time as the mixing time scale. The internal mixing pattern, complete mixing time, and the volume participating in complete mixing were obtained for the UASB test with hydraulic retention time (HRT)=5, 6, 8, and 10 h by model calculation to analyze the sludge-water mixing process. Its mixing achieved that of a CSTR under higher hydraulic load, and that of a series connected two-stage CSTR in advective diffusion mode under lower hydraulic load. The model analysis for the reported internal reflux packed-bed anaerobic reactor with HRT=72, 48, 24, 12, 6, and 0.25 days showed that there existed mixing time scales shorter than the minimum reflux cycle time adopted in the test, in which the transport of the reflux alone made the sludge-water mixing and reaction stably equivalent to that of a CSTR. Both test reactors achieved CSTR at a lower mixing intensity with a velocity of 0.40–0.80 m/h and complete mixing time scale of 1.0–1.9 h for the UASB and an available velocity of 5.0 m/h and complete mixing time scale of 0.15 h for the internal reflux packed-bed anaerobic reactor.