Low-Frequency Ripple Voltage Suppression Based on Active Power Decoupling for Modular Multilevel Converter Sub-Module Capacitors

The modular multilevel converter (MMC) is emerged as the most favourable multilevel converter topology for medium to high-voltage applications. Reliability is one of the major concerns in an MMC due to high fragile component count. Due to low-cost and high energy density, electrolytic capacitors (ECs) are usually preferred as floating capacitors in the MMC. However, the ECs are gradually degraded over the time due to inherent chemical processes, which results in a decrease in capacitance value. This results in an increase in voltage ripple across the SM capacitors and would distort the output waveforms. Moreover, the prolonged use of these aged capacitors could disrupt the MMC operation. Therefore, monitoring and failure detection of submodule (SM) capacitors in an MMC are pivotal to enhance the reliability. This paper presents an SM capacitance estimation strategy for an MMC using nearest level modulation (NLM). A modified voltage balancing control structure with NLM is presented to reduce the unbalance in the capacitor voltages. The proposed approach uses available hardware for converter control with easy implementation in the same controller. Extensive studies are conducted on a three-phase MMC in PLECS simulation platform. Furthermore, experimental results are presented to substantiate the effectiveness of the proposed approach.

This paper proposes a new strategy for balancing the Capacitor Voltages (CVs) for Modular Multilevel Converters (MMCs). The balancing is one of the main challenges in MMC applications and it is usually solved by adopting a global arm control approach. For performing such an approach, a sorted list of the SubModules (SMs) according to their capacitor voltages is required. A common way to accomplish this task is to implement a sorting algorithm in the same controller used for the modulation technique. However, the execution time and the computational efforts of these kinds of algorithms increase very rapidly when the number of SMs grows. A novel idea is presented in this paper by using a mapping strategy that directly stores in a ranked list the SMs according to the measured CVs. Avoiding the use of sorting algorithms leads to a considerable reduction of the execution time as well as the computational efforts.

The modular multilevel converter (MMC) is one of the most promising topologies for high- and medium-voltage applications. However, the conventional MMC relies on large arm inductance and complicated feedback control to maintain submodule (SM) capacitor voltages balanced, which requires a large number of voltage sensors and complicated arm current control loops. In contrast to the conventional perspective, the MMC can be regarded as a derivative from the general multilevel topology based on switched-capacitor (SC) structure. The SC structure endows excellent properties to the MMC, such as minimum or no arm inductor and automatic SM capacitor voltage balancing capability. This MMC with minimum or no arm inductor is named as SC-MMC. Since the arm inductances are very small, the SM capacitor voltages can be balanced automatically. Small stray/parasitic inductance is enough to limit inrush current during SM's switching instants to the rated current level. To unleash the automatic SM capacitor voltage balancing capability of the SC-MMC, a Y-matrix modulation (YMM) has been proposed, which does not require closed loop control or any sensor, has no limitations on the number of SMs, and works for both half-bridge and full-bridge SMs. An unresolved issue of the emerging YMM is that, in the published literature, the existence of the Y matrix with full rank has not been proved theoretically beyond the observation for the SC-MMC when the number of SMs is large. In this paper, an analytical proof of the existence of the full rank Y matrix is provided, which implies the automatic voltage balance of SMs for the MMC with arbitrary number of SMs in each arm. Simulation results using the YMM on a 21-level SC-MMC with minimum arm inductance are provided to verify the voltage balance theory/observation of the SC-MMC using the YMM.

— The modular multilevel converter (MMC) is considered to be emerging multilevel topology for medium to high power applications due to its modularity and highly reliable structure. However, large submodule (SM) capacitor voltage ripple and higher circulating current during variable frequency operation is the major drawback of the MMC. In the literature, higher-order harmonic elimination technique is presented to reduce SM capacitor voltage ripple and circulating current. In this article, effect of lower-order harmonics on circulating current is investigated. The effect of second-order fundamental frequency current harmonic I2f on arm inductor is analyzed. Based on detailed analysis, an optimal design method for selection of arm inductor is proposed. Proposed optimal design is capable of reducing the circulating current under variable frequency range as well as SM capacitor voltage ripple remains under specified limit during entire variable frequency operation. A detailed MATLAB model of MMC fed high power medium voltage drive is developed. Experimental setup is also developed to check the effectiveness of proposed optimal design method. Reduction in circulating current and control of SM capacitor voltage ripple is observed for entire range of frequency.

To provide ancillary services in HVDC applications, modular multilevel converters (MMCs) with integration of energy storage systems are a promising solution as they take advantage of the modularity and the controllability of the stored energy. In these solutions, an energy storage system is connected to the DC capacitor of a submodule (SM) to make an energy storage submodule (ES-SM). An MMC with partial integration (MMC-PIES) is an MMC with each arm made of a mix of SMs and ES-SMs. In this paper, we propose a novel design methodology for these converters considering they are built based on existing prebuilt submodules, while design methodologies in the literature consider the SM and ES-SM characteristics to be degrees of freedom. Therefore, the proposed approach is closer to an industrial standpoint and computes the minimum number of ES-SMs to comply with requirements. We also include a new optimization method for the circulating currents needed to balance the energy in the SM and ES-SM capacitors. Design scenarios are presented. The results show that the value of the DC capacitance and the current limitation of the switches highly influence the design, restricting the possible operating points. In addition, half-bridge ES-SMs seem to be a more promising solution than full-bridge ES-SMs, reducing the number of ES-SMs.

Low-speed drive is one of the challenges for modular multilevel converters (MMCs) due to large capacitor voltage fluctuation. In this article, a cascaded MMC and cycloconverter (CCV) based machine drive system is proposed to ensure stable operation of medium-voltage and low-speed machine. The MMC provides medium-frequency ac voltage for the CCV, and the CCV converts the medium-frequency ac input to low-frequency ac output required by the machine. Detailed analysis about MMC's operation frequency, device current stress, and submodule (SM) capacitance are given in this article. Proposed drive system can operate at zero/low frequency under rated load torque, while the SM capacitance is much smaller than that in existing methods. Simulation and experimental studies are conducted, and the results verify the effectiveness of the proposed system.

The modular multilevel converter (MMC) has become the most attractive converter technology for medium/high-power applications, specifically for high-voltage dc (HVdc) transmission systems. One of the technical challenges associated with the operation and control of the MMC-based system is to precharge the submodule (SM) capacitors to their nominal voltage during the startup process. In this paper, considering various SM circuits, a generalized precharging strategy is proposed for the MMC-based systems, which can implement soft startup from the dc or ac side. The proposed precharging strategy can be applicable for various SM circuits and MMC configurations. The proposed startup strategy does not require extra measurements and/or auxiliary power supplies. The charging current is controlled by adjusting the changing rate of the number of blocked and bypassed SM capacitors. Based on the proposed startup strategy, the startup processes of MMC/MMC-HVdc systems with various SM circuits are analyzed and a generalized startup procedure for various MMC-HVdc systems is proposed. In addition, the uncontrollable steady-state SM capacitor voltages of various MMC-based systems are analyzed and the associated precharging time is also investigated. Performance of the proposed strategy for various MMC-HVdc systems is evaluated based on time-domain simulation studies in the PSCAD/EMTDC software environment and experimental results are based on a scaled-down prototype.

Modular multilevel converters (MMCs) are very promising and attractive in medium-/high-voltage applications. One of the main technical challenges associated with MMCs is to precharge all submodule (SM) capacitors to their nominal voltage values during a startup process. This article proposes a simple and effective startup strategy for MMCs based on a deadbeat predictive current control. This strategy can realize a fast precharge for all the SM capacitors from either ac-side or dc-side main voltages without any inrush current and, thus, guarantees a rapid and safe startup of MMCs. With the developed strategy, precharge currents from both ac-side and dc-side can be easily regulated in a closed-loop manner with an excellent dynamic performance. Moreover, conventional controller design and parameter tuning are not necessary, which greatly reduces design burdens and structural complexities of the control algorithm, and consequently facilitates its implementations. Detailed design processes and considerations of the proposed startup strategy are introduced and analyzed. The effectiveness and performance of the developed strategy are verified by sufficient experimental results.

Summary form only given. The modular multilevel converter (MMC) is a potential candidate for medium/high-power applications, specifically for high-voltage direct current (HVDC) transmission systems. One of the technical challenges associated with the control of an MMC is to carry out the submodule (SM) capacitor voltages balancing task without imposing any unnecessary switching transition among the SMs. This paper develops a general framework for the capacitor voltage balancing of an MMC. Based on the developed framework and with the objective of reducing the unnecessary switching transitions among the SMs, three capacitor voltage-balancing strategies are proposed and investigated: 1) a slow-rate balancing strategy based on the conventional sorting method; 2) a hybrid balancing strategy which combines a predictive method with the conventional sorting method; and 3) a fundamental-frequency balancing strategy. Performance of the proposed strategies for a point-to-point 21-level MMC-based HVDC system is evaluated based on time-domain simulation studies in the PSCAD/EMTDC software environment. The reported study results demonstrate the capability and tradeoffs of the proposed strategies to reduce the number of switching transitions and, consequently, the MMC losses, under various conditions.

A large high-voltage direct current (HVdc) reactor is required in modular multilevel converter (MMC) projects to realize dc fault current limiting (FCL). This condition may result in adverse effects on MMC control dynamics and oscillation and instability of HVdc systems. In this article, a virtual reactor (VR) control strategy is proposed to reduce a fixed large HVdc reactor. The VR characteristic of MMCs is revealed and analyzed as a controlled reactor, and the inductance of this reactor can be directly controlled by the discharge degree of submodule capacitors. A virtual reactor fault current limiting (VRFCL) control strategy in which VR can effectively limit dc fault current and substitute the fixed HVdc reactor is proposed accordingly. Simulation and experimental results verify the proposed control strategy. The adoption of the proposed strategy can eliminate the undesirable effect caused by an HVdc reactor, and the sub-module (SM) capacitor voltage can be reserved well. In addition, fault clearance time and fault energy dissipation can be reduced. The proposed VRFCL control is beneficial for MMCs to safely ride through dc fault in a continuous operation manner.

Modular Multilevel Converter (MMC) has been widely used in medium/high voltage direct current transmission, motor drive, and renewable energy power generation, etc. The reliability requirements of MMC system which is composed of sub-modules(SM) as building blocks, are getting crucial. However, the testing for reliability of SMs in a full MMC system is time consuming and costly. In this paper, a mission profile emulator for SMs in MMC system is therefore focused, by using this mission profile emulator, the SMs can be tested individually without building a full MMC system. Simulation results show that the mission profiles of the SM under test is well agrees with the SM in a complete MMC system.

To achieve higher reliability in the modular multilevel converters (MMC) for HVDC transmission systems, the internal condition of the DC capacitors of the submodules (SM) needs to be monitored regularly. For an online estimation of the SM capacitance, a controlled AC current with double the fundamental frequency is injected into the circulating current loop of the MMC, which results in current and voltage ripples in the SM capacitors. The capacitor currents are calculated from the arm currents and their switching states. By processing these AC voltage and current components with digital filters, their capacitances are estimated by a recursive least square (RLS) algorithm. The validity of the proposed scheme has been verified by simulation results for a 300-㎿, 300-㎸ HVDC system. In addition, its feasibility has been verified by experimental results obtained with a reduced-scale prototype. It has been shown that the estimation errors for both the simulation and experimental tests are 1.32% at maximum.

To further improve the power supply sustainability of the ac/dc hybrid distribution networks, this article proposes a control strategy for the modular multilevel converter (MMC) under grid-side open-circuit fault, which is based on independent arm current control. Firstly, the behaviors of the MMC after the faults are analyzed, including single-phase and two-phase open-circuit faults. For single-phase open-circuit fault, the proposed strategy can be achieved by reconfiguring the amplitude and phase of the arm currents, thereby eliminating the zero-sequence current. For two-phase open-circuit fault, both the arm currents and voltages need to be reconfigured. After that, a method for detecting and locating specific faults is provided, which can be implemented by detecting the amplitude of the zero-sequence current. Besides, the postfault characteristics of the MMC under single-phase open-circuit condition are given, including submodule (SM) capacitor voltage ripple, circulating current, arm rms current and arm peak current. According to it, long-term postfault operation of the MMC can be guaranteed with 50% of the rated power. Additionally, stable dc-bus voltage and balanced SM capacitor voltage are satisfied even though one phase is disconnected. Moreover, with the proposed control strategy, although the MMC is able to operate for a short period of time in emergency situations when two phases are disconnected, it is not supposed to transmit power due to the inevitable large current on neutral conductors. Finally, the feasibility and effectiveness of the proposed control strategy is validated by simulation and experimental results.

The modularity, fault-tolerability, and voltage scalability features allow the modular multilevel converter (MMC) to be a promising topology for modern electric ship applications. Arm voltage and submodule (SM) capacitor voltage balancing controllers with conventional high-frequency modulation schemes are indispensable for reliable and stable operation of an MMC. This requires an additional external arm controller and the control complexity increases for an MMC with a large number of SMs. Alternatively, the space-vector pulse width modulation (SVPWM) schemes provide more freedom in selecting the voltage vectors to achieve multiple objectives, thus eliminating the arm voltage balancing controller. In this paper, a simplified SVPWM implementation for an $n$ -level MMC is proposed. This scheme utilizes all the available switching states and calculates switching timings by mapping to a two-level space-vector structure. The computational burden of the proposed scheme is independent of converter voltage level, therefore it is computationally efficient and well suited to the MMC with any number of SMs. Experimental results are presented to show the performance of an MMC system using the proposed scheme under steady-state, rapid acceleration and speed-reversal conditions.

With the increasing application of the modular multilevel converter (MMC), diagnosis of submodule (SM) open-circuit failures is becoming a popular topic. SM open-circuit failure diagnosis normally requires failure detection and failure localization. Almost all existing SM open-circuit failure diagnosis methods execute failure detection and failure localization separately. This not only complicates the diagnosis process, but also results in longer diagnosis time. In this paper, an SM open-circuit failure diagnosis method enabling combined failure detection and localization is proposed. The proposed method is established based on the characteristics that capacitor voltages of faulty SMs variate differently from those of normal SMs. A quantification index of capacitor voltage variation is first proposed. By evaluating the corresponding index values of all SMs with the quartile analysis, failure detection and localization can be implemented simultaneously. What’s more, the quartile analysis results can also identify faulty switching devices in the SM, which provides more flexibility for failure tolerant control. The proposed method performs relatively easy and requires no extra hardware resources. Meanwhile, both single and multiple failures can be properly handled whether faulty SMs are in the same or different arms. Besides, the proposed method is immune to parameter uncertainties owing to its statistical property. Experimental results under various failure scenarios are presented to verify the effectiveness of the proposed method.