Low-noise, low-power, event-driven read-out of counting Pixel Array Detectors

In present day technology there is an immense need of developing suitable data communication interfaces for real time embedded systems.Field Programmable Gate Array (FPGA) offers various resources, which can be programmed for building up an efficient embedded system.In recent years the SOC (System on Chip) design eg, in media processing [1] is becoming more and more important in real time embedded applications as SOCs require low power, low area but are still capable of implementing various complex functionalities.In order to achieve SOC architecture, which can run a real time application, we need to develop high-speed data interfaces of the system with the external world through its various I/O ports.The DMA controller, which sends the data from I/O to memory and vice-versa without intervention of the processor, thus plays a vital role in these systems in order to achieve faster I/O data transfer.This paper proposes a technique to implement a DMA controller core on Spartan 3A FPGA hardware, which serves as an essential component for developing a real time data acquisition and processing system.

Inspired by the success of BitTorrent (BT) in the field of file sharing, in this paper, we present a peer-to-peer (P2P) video-on-demand (VoD) system based on asynchronous data transfer. The system is specified with centralized directory and unstructured overlay. For efficient supplier selection and data transfer among peers, we consider the rareness and the priority of video blocks as well as available network resource. Packet-level simulations show the benefits of cooperated asynchronous data transfer in terms of playback continuity, launch delay and server stress.

The JUNGFRAU 4-megapixel (4M) charge-integrating pixel-array detector, when operated at a full 2 kHz frame rate, streams data at a rate of 17 GB s-1. To operate this detector for macromolecular crystallography beamlines, a data-acquisition system called Jungfraujoch was developed. The system, running on a single server with field-programmable gate arrays and general-purpose graphics processing units, is capable of handling data produced by the JUNGFRAU 4M detector, including conversion of raw pixel readout to photon counts, compression and on-the-fly spot finding. It was also demonstrated that 30 GB s-1 can be handled in performance tests, indicating that the operation of even larger and faster detectors will be achievable in the future. The source code is available from a public repository.

This work aims to investigate the FPGA (Field-Programmable Gate Array) and GPU (Graphical Processing Unit) technology in image optimization research for an industrial frontier study. Using an experimental method, the research compared the efficiency of two technologies as implemented in some many image processing algorithms. NI CompactRIO platform for FPGA implementation and NVIDIA GeForce GTX 970 in GPU processing performed differently. As is well known, low-lag applications (camera synchronization, real-time data processing etc.) were very well suited for FPGAs. GPUs with architecture CUDA, on the other hand could be a thousand times faster than traditional CPUs in parallel data processing. Other challenges identified through analysis were FPGA design optimization and GPU resource wise utilization. The results give recommendation in terms of selecting technologies based on the features for image industrial processing applications

A data Acquisition (DAQ) and control system is being developed for a pixel array detector that will be used for a single-particle scattering experiment at the linac coherent light source (LCLS). The experiment requires that sub-picosecond pulses of 8 kEV X-rays are scattered off single particles 120 times a second. The scattered X-rays are converted to charge in a 2-dimensional pixelated diode array. The charge is integrated on to the 760times760 pixel detector readout chip and digitized in-pixel. The full detector is composed of tiled 185times192 pixel readout chips. The DAQ and control system provides low-level control of the integration and read-out processes, sets the detector mode of operation, addresses the pixels and transfers the data to high-speed local storage. Low-level data processing such as reordering, frame formatting and data averaging may also be required before data transfer. The DAQ and Control system is designed in a hierarchical and modular manner using a Xilinx XC4V100FX FPGA based DAQ board and is user controlled and monitored in software using master/slave command handshaking across the PCI Express bus. This allows for a very customized yet interactive and flexible system while sustaining a data throughput to disk in excess of 1.1 Gbps. Full speed detector control and data acquisition have been achieved for a single module chip CMOS ASIC (192times185 pixels) using the system described. Simultaneous to data acquisition, the DAQ and control system will also provide low-latency data transfer to a remote massive storage system on 10 GbE.

Field-programmable gate arrays (FPGAs) have garnered significant interest in research on high-performance computing because their computation and communication capabilities have drastically improved in recent years due to advances in semiconductor integration technologies that rely on Moore's Law. In addition to improving FPGA performance, toolchains for the development of FPGAs in OpenCL have been developed and offered by FPGA vendors that reduce the programming effort required. These improvements reveal the possibility of implementing a concept to enable on-the-fly offloading computation at which CPUs/GPUs perform poorly to FPGAs while performing low-latency data movement. We think that this concept is key to improving the performance of heterogeneous supercomputers using accelerators such as the GPU. In this paper, we propose an OpenCL-enabled data movement method to directly access the global memory of the GPU and show how to implement cooperative GPU-FPGA computation using it. The results of experiments show that our proposed method can achieve a latency of 0.59 µs and a data transfer rate as high as 7.0 GB/s between the GPU and the FPGA, thus confirming that it is effective at realizing high-performance cooperative GPU-FPGA computation.

WASMII is a virtual hardware system that executes dataflow algorithms. It is based on an MPLD (Multifunction Programming Logic Device), an extended FPGA (Field Programmable Gate Array) that implements multiple sets of functions as configurations of a single chip. An algorithm to be executed on WASMII is written in the DFC dataflow language and then translated into a collection of FPGA configurations, each representing a page-sized subgraph of the dataflow graph. Although we have developed an emulation system and software environment for WASMII, it has tended to be an unrealistic system due to the difficulty of the MPLD implementation. However with recent technologies of semiconductors, FPGA and DRAM can be implemented into a single LSI chip. By using the column buffer of the DRAM array as a configuration memory of an FPGA, replacement of configuration data can be done almost the same speed as an MPLD. Compared with the MPLD approach, a large amount of data can be stored in the integrated DRAM. Initial simulation results show that such a chip can almost save the loss caused by data transfer from the off chip memory of original WASMII.

Among various nanometer-level displacement measurement methods, grating interferometry-based linear encoders are widely used due to their high robustness, relatively low cost, and compactness. One trend of grating encoders is multi-axis measurement capability for simultaneous precision positioning and small order error motion measurement. However, due to both lack of suitable hardware data processing platform and of a real-time displacement calculation system, meeting the requirements of real-time data processing while maintaining the nanometer order resolutions on all these axes is a challenge. To solve above-mentioned problem, in this paper we introduce a design and experimental validation of a field programmable gate array (FPGA)-cored real-time data processing platform for grating encoders. This platform includes the following functions. First, a front-end photodetector and I/V conversion analog circuit are used to realize basic analog signal filtering, while an eight-channel parallel, 16-bit precision, 200 kSPS maximum acquisition rate Analog-to-digital (ADC) is used to obtain digital signals that are easy to process. Then, an FPGA-based digital signal processing platform is implemented, which can calculate the displacement values corresponding to the phase subdivision signals in parallel and in real time at high speed. Finally, the displacement result is transferred by USB2.0 to the PC in real time through an Universal Asynchronous Receiver/Transmitter (UART) serial port to form a complete real-time displacement calculation system. The experimental results show that the system achieves real-time data processing and displacement result display while meeting the high accuracy of traditional offline data solution methods, which demonstrates the industrial potential and practicality of our absolute two-dimensional grating scale displacement measurement system.

In this paper we introduce a new real-time parallel image processing system based on an IEEE1394-based PC-cluster. PC-clusters are becoming standard tools in the field of computer vision, especially for real-time multi-view image processing. To reduce the cost of system construction, we have employed IEEE1394 bus as a base network of the PC-cluster. IEEE1394 bus has the throughput of up to 400Mbps, which is large enough to transfer uncompressed video data, and supports not only asynchronous data transfer but isochronous one, which is inevitable for real-time data transfer. In addition, since we have several products of IEEE1394-based digital cameras, we can easily integrate real-time image processing system including camera systems. This paper presents an overview of our real-time parallel image processing system on an IEEE1394based PC-cluster, referring to basic features of IEEE1394. We also show some experimental results to evaluate the performance of the PC-cluster, comparing it with the performance of our previous Myrinet-based PC-cluster. Then we show a prototypical application of the system, which is real-time volume reconstruction from multi-view images by visual cone intersection method.

In the digital era, data is one of the most important assets since it conceals valuable information. Developers of data-intensive systems have new challenges at each level of streaming, storing, and processing large quantities of data in a variety of forms and speeds. Obtaining useful information at the proper time and place is also crucial. Since the value of information is inversely proportional to time, real-time data processing and analytics are receiving more attention. Due to the importance of real-time data processing and analytics, this study focuses on real-time data processing concepts and terminology, popular technologies used in real-time data processing and analytics, popular NoSQL storage technologies used in real-time data processing, and real-time data processing application areas. The purpose of this paper is to provide researchers of real-time analysis and developers of data-intensive systems with a comparative perspective on real-time data processing by highlighting the key characteristics of real-time data processing technologies, NoSQL storage technologies, their application domains, and selected examples from previous studies.

This paper presents a systematic approach for automatic generation of look-up-table (LUT) for function evaluations and minimization in hardware resource on field programmable gate arrays (FPGAs). The class of functions supported by this approach includes sine, cosine, exponentials, Gaussians, the central B-splines, and certain cylinder functions that are frequently used in applications for signal and image processing and data processing. In order to meet customer requirements in accuracy and speed as well as constraints on the use of area and on-chip memory, the function evaluation is based on numerical approximation with Taylor polynomials. Customized data precisions are supported in both fixed point and floating point representations. The optimization procedure involves a search in three-dimensional design space of data precision, sampling density and approximation degree. It utilizes both model-based estimates and gradient-based information gathered during the search. The approach was tested with actual synthesis results on the Xilinx Virtex-2Pro FPGA platform.

The high processing speed and reconfigurable features of FPGA (Field-Programmable Gate Array) make it the first choice for acceleration chip. Currently, the CPU/FPGA hybrid architecture is a research hotspot in improving hardware processing speed. Many companies have investigated in related researches. However, the current researches have not solved the coordination problem between CPU and FPGA in this architecture. The Communication efficiency problem between CPU and FPGA is the key to the failure of hardware performance. Some of the current researches are mainly to optimize the communication protocol between CPU and FPGA to improve data transfer rate. This paper proposes a different method to reduce the frequency of communication between CPU and FPGA for this problem. The processing speed of the architecture is improved by simplify communication between the CPU and the FPGA. This approach reduces communication frequency between the CPU and the FPGA by splitting the software into hardware master thread and slave threads that can run independently run on the FPGA. The CPU only needs to configure the FPGA at the beginning and retrieve the result from the FPGA at the end. No communication is required during FPGA running, thereby reducing unnecessary communication waste.

The development of a low-cost high-performance secure hash algorithm (SHA)-256 accelerator has recently received extensive interest because SHA-256 is important in widespread applications, such as cryptocurrencies, data security, data integrity, and digital signatures. Unfortunately, most current researches have focused on the performance of the SHA-256 accelerator but not on a system level, in which the data transfer between the external memory and accelerator occupies a large time fraction. In this paper, we solve the state-of-art problem with a novel SHA-256 architecture named the multimem SHA-256 accelerator that achieves high performance at the system on chip (SoC) level. Notably, our accelerator employs three novel techniques, the pipelined arithmetic logic unit (ALU), multimem processing element (PE), and shift buffer in shift buffer out (SBi-SBo), to reduce the critical path delay and significantly increase the processing rate. Experiments on a field-programmable gate array (FPGA) and an application-specific integrated circuit (ASIC) show that the proposed accelerator achieves significantly better processing rate and hardware efficiency than previous works. The accelerator accuracy is verified on a real hardware platform (FPGA ZCU102). The accelerator is synthesized and laid out with 180 nm complementary metal oxide semiconductor (CMOS) technology with a chip sized <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8.5\,mm \times 8.5\,mm$ </tex-math></inline-formula> , consumes 1.86 W, and provides a maximum processing rate of 40.96 Gbps at 80 MHz and 1.8 V. With FPGA Xilinx 16 nm FinFET technology, the accelerator processing rate is as high as 284 Gbps.

Convolutional neural network (CNN) accelerator has been gradually deployed on edge Field-Programmable Gate Arrays (FPGAs) for satellite remote sensing. However, the considerable complexity of software/hardware co-design inhibits the development of data processing applications on edge FPGAs. Moreover, the performance of edge FPGAs is restricted due to limited bandwidth and excessive software/hardware communication overhead in satellite remote sensing. To reduce co-design complexity, we propose a software/hardware data mapping framework for the deployment efficiency of the remote sensing data accelerator, called Fast-Pipe. Especially the software design of Fast-Pipe takes into account the interaction requirements of accelerator deployment and the poll and copy latency of data transfers. The data transfer driver is implemented in the user space to reduce latency with a new scheduling method and an interrupt policy for sending and receiving data. Meanwhile, an associated hardware structure is designed with Direct Memory Access (DMA) to implement data scheduling and mapping. With Fast-Pipe, the data in the software buffer is mapped into multiplexed data streams. Experimental results show that Fast-Pipe speed up 46.38× in small data transfer, and average 2× higher in large data transfer than previous work with stable data transfer speed.

&lt;p&gt;In this paper, a differential robot is designed and controlled by PCI card. This card connected between personal computer and microcontroller. Furthermore PID controller was designed by Asic device and implemented on robot.&lt;/p&gt;&lt;p&gt;In this paper, instead of using that massive hardware’s, it designed a single FPGA chip to perform the same motion control of robot wheels. We developed a general purposed motion control of robot using a field programmable gate array (FPGA).&lt;/p&gt;&lt;p&gt;In order to obtain independent robots movement, the main PID controller is implemented with a Field Programmable Gate Array. The main PID controller routine was designed to be fairly general purpose and modular form. While it is used to control a DC motor, it could be re-deployed to other situations where some parameter has to be controlled to a set value under varying conditions. The actual control software is located in a single function and its major inputs and output are held in a structure. Although it was designed originally for a specific job it is really only intended as an example of the basic techniques involved and to allow those with no control system knowledge to experiment with a simple PID system.&lt;/p&gt;&lt;p&gt;, FPGA, ATmega128L, Robot, Digital.&lt;/p&gt;