Low-Power and High-Density Dynamic Random Access Memory

Refresh operations consume substantial energy and bandwidth in high-density dynamic random-access memory (DRAM) memory. The trend of increasing refresh overhead limits the scalability of DRAM memory that refreshes all cells at the same rate, because the refresh rate setting depends on the worst-case weak cell manufactured in unstable process technology. To cope with this issue, fine-grained refresh (FGR) is proposed to eliminate the unnecessary refresh operations caused by minor weak cells. Even JEDEC's DDR4 DRAM specification announces the support of FGR, which is likely to evolve and become a standard in future DRAM. Unfortunately, according to our key observation, the effectiveness of FGR is greatly confined by the procedure of refresh-oblivious device integration because all memory devices within a module have to be controlled and refreshed in a lockstep way after the step of assembly. In this paper, we are the first to propose a holistic FGR-oriented DRAM optimization framework, retention-aware DRAM assembly and repair (RADAR), to enhance the effectiveness of FGR in DRAM modules. RADAR includes two novel techniques applicable at the stage of DRAM assembly. The first one is retention-aware device clustering that integrates the “compatible” devices to achieve low refresh rate through a preassembly testing and retention-aware matching method. The second technique, Microfix, exploits the hierarchical DRAM array structure and its redundancy to fix critical weak DRAM rows through fine-grained row and subarray remapping. With this optimization architecture, RADAR, the refresh overhead of DRAM dual in-line memory modules can be dramatically reduced as implied in the experiments.

Traditional Dynamic Random Access Memory (DRAM) technology faces significant scaling challenges as device dimensions approach fundamental physical constraints. Indium-gallium-zinc-oxide (IGZO) has emerged as a potential solution to these scaling limitations, offering advantageous characteristics such as ultra-low leakage currents and compatibility with low-temperature fabrication processes. This paper reviews recent advancements in Two-Transistor Zero-Capacitor (2T0C) DRAM technology that utilize IGZO materials, with a focus on innovations in device architecture and system-level integration.

This paper proposes an uncertainty quantification (UQ)-incorporated design optimization technique that integrates UQ considering the statistical characteristics of sensing margin with machine learning (ML) for the design of bitline sense amplifiers (BLSAs) in dynamic random access memory (DRAM), including offset compensation operation. The increased offset due to process variation exacerbated by device scaling degrades the reliability of DRAM read operations, making quantitative analysis of process variation essential. Conventional Monte Carlo (MC)-based UQ analysis provides high accuracy but requires extensive simulation costs. Accordingly, this study systematically defines key input and output variables for conventional BLSA and two representative offset compensation BLSA structures, introduces Sobol sequence-based quasi-Monte Carlo (QMC) sampling to improve simulation efficiency, and generalizes the Standard UQ methodology to predict statistical distributions of circuit performance parameters under process variation. Furthermore, a 3-Stage UQ algorithm that sequentially learns nominal, mean, and standard deviation values is proposed to enhance the efficiency of ML model training. HSPICE simulation results based on the TSMC 65 nm process demonstrated that the proposed 3-Stage UQ method reduced the simulation time required for ML training data generation by an average of 43% compared to the Standard UQ method and achieved excellent prediction performance even in data-limited environments. Additionally, design optimization combined with Bayesian Optimization (BO) confirmed performance improvements across all circuit structures. The methodology presented in this study enables effective process variation-aware optimization for DRAM designs requiring high reliability and yield, and is expected to contribute to next-generation memory circuit design automation.

Journaling techniques play an important role in addressing the reliability issue of filesystems caused by the volatile dynamic random access memory (DRAM)-based buffer cache. However, journaling techniques introduce a large number of extra storage writes, which greatly degrades system performance, especially for mobile devices. Emerging nonvolatile memory (NVM) technologies bring a new perspective of solving the write amplification issue caused by journaling. By adopting NVM as the buffer cache, the committed data can be maintained in NVM before being written back to the storage, thus, eliminating the journaling overhead. However, simply utilizing NVM as the buffer cache suffers from the limited lifetime and the relatively longer write latency of NVM. In this paper, we present a hybrid buffer cache architecture, named UniBuffer, by combing NVM with dynamic random access memory (DRAM) to reduce the journaling overhead and overcome the inherent constraints of NVM. In UniBuffer, we first propose a journaling-aware page management (JAPM) policy to smartly allocate data to DRAM and NVM pages. JAPM puts infrequently updated data in NVM to reduce the journaling overhead and frequently updated data in DRAM to improve the write performance and lifetime of the hybrid buffer cache. In addition, since data in one journaling transaction may be dispersed in NVM and DRAM simultaneously, different committing policies are required for different storage media, respectively. In order to guarantee the atomicity of the transaction execution in the hybrid cache architecture, a partial in-place commit (PIPC) journaling scheme is proposed to coordinate different committing patterns for NVM and DRAM. We have implemented the proposed techniques on Linux 3.14.52 and measured the performance with representative I/O-intensive benchmarks. The experimental results show that our scheme effectively improves the I/O performance compared with the ext4 filesystem and prolongs the lifetime of the hybrid buffer cache compared with the union of buffer cache and journaling (UBJ) scheme.

The authors discuss a 4-Mb substrate-plate-trench (SPT) DRAM (dynamic random access memory) technology applying an innovative manufacturing test strategy using the technology product chip, an addressable diagnostic monitor (ADM), and trench DC macroarray test structures. This manufacturing functional test strategy is effective in achieving process optimization, defect characterization, and high retention yield in a DRAM trench technology. Examples of the strategy's application in various situations and at different development stages are shown. >

Dynamic random access memory (DRAM) devices are used to handle data transfer to and from the microprocessors in a computer or server. Traditionally, the speed of the memory devices has lagged behind that of the microprocessors. With the advent of high-speed microprocessors such as Intel's Pentium 4 and AMD's Athlon, the speed of DRAM has also increased from below 100 MHz to near 1 GHz. At the same time, memory chip density has increased from 512 Kbit to 256Mb or higher. To package the new generation of high-density devices, new packaging technology such as chip scale package (CSP) is being applied to replace SOJ and TSOP packages. This paper reviews the progress in memory technology and its applications, including Synchronous Dynamic Random Access Memory (SDRAM), Rambus DRAM (RDRAM), and Double Data Rate (DDR) SDRAM. Packaging technology used for these devices, including conventional TSOP, stacked TSOP and chip scale packages such as μBGA and memory BGA (mBGA) for Rambus and DDR are discussed. The surface mount technology (SMT) manufacturing process of Dual In-line Memory Modules (DIMM) is described. Experimental results on solder printing and reflow profile condition optimization for the DIMM modules are discussed in detail by comparison of the resulting microscopic solder joint grain structures.

This article presents a low random noise, a low-power, and a high-speed 2-mega pixels (Mp) global-shutter (GS)-type CMOS image sensor (CIS) using an advanced dynamic random access memory (DRAM) technology. GS CIS is one of the alternatives to solve image distortion issues caused by a conventional rolling-shutter (RS) CIS operation, since a 2-D image data can be simultaneously sampled by the in-pixel analog memory. To achieve a high-performance GS CIS, we proposed a novel architecture for digital pixel sensor (DPS) which is a high-speed GS operation CIS with a pixel-wise analog-to-digital converter (ADC) and an in-pixel digital memory. The major technologies of the proposed DPS can be summarized as follows: 1) two large coupling capacitors with mature DRAM technology; 2) extremely narrow pitch Cu-to-Cu (C2C) bond; and 3) finally low-powered ADC with a near sub-threshold operation. A perfect auto-zero operation for ADC is implemented using two DRAM capacitors, and a large number of transistors have to be integrated in the single pixel for realizing pixel-level ADC. Thus, each pixel has two fine-pitch C2C interconnections. This makes it possible to realize wafer-level stacked unit pixel. The proposed DPS with low-power consuming analog circuits has been successfully designed and developed for extremely fast-readout speed of max. 1200 frames per second (fps) and high sensitivity for low-illumination conditions.

A dynamic oxide semiconductor random access memory (DOSRAM) array that achieves reduction in storage capacitance (Cs) and decrease in refresh rate has been fabricated by using a c-axis aligned crystalline oxide semiconductor (CAAC-OS) transistor (L = 60 nm) with an extremely low off-state current. We have confirmed that this array, composed of cells that include a CAAC-OS transistor with W/L = 40 nm/60 nm using InGaZnO and a 3.9 fF storage capacitor, operates with write and read times of 5 ns. Therefore, DOSRAM can ensure sufficient Cs while maintaining operation speed comparable to that of dynamic random access memory (DRAM). We have found that the read signal voltage of DOSRAM is changed by approximately 30 mV after 1 h at 85 °C. Thus, DOSRAM is a promising replacement for DRAM.

Dynamic random access memory (DRAM) is one key component in modern electronic systems. In this paper, we propose a software-hardware-cooperated built-in self-test (SHC-BIST) scheme for the channel-based DRAMs. The testing of DRAMs consists of two major phases: DRAM initialization and DRAM array testing. Typically, the DRAM initialization process is short and executed in the beginning of the DRAM array testing. Thus, it is inefficient to realize it using the dedicated BIST hardware. On the other hand, it is not time efficient if we use the processor (software) to execute the DRAM array testing. Therefore, the SHC-BIST scheme uses a programmable BIST circuit to execute the DRAM array testing and takes advantage of the processor to execute the DRAM initialization and control the programmable BIST circuit such that the test time and hardware cost can be minimized. We verify the SHC-BIST scheme using a system with a LEON3 processor and a multi-channel DRAM.

Anomalous currents (I) in worst-bit cells in high-density dynamic random-access memories are theoretically analyzed with temperature (T) as a parameter. And activation energy (Ea) is evaluated from the slopes of (log I) versus (1/T) plots. It is found that the anomaly in Ea as a function of applied bias (V), i.e., a steep decrease and saturation in Ea–V curves, can be clearly explained by introducing spatial locality in the deep-trap distribution. Moreover, it is shown that the anomaly in Ea–V curves occurs synchronously with an anomaly of current; i.e., a steep increase and saturation in I–V curves. Simulated electron-hole distributions clarify the physical mechanism of these anomalies; that is, when applied reverse bias is low and the spatially localized deep traps are outside of the depletion layer, Ea is near Eg because of electrical nonactivity of deep traps. And when applied reverse bias is high and the deep traps are spatially included in the depletion layer, carriers generated from deep-trap centers dominate the carrier transport and Ea is around the energy level (Et) of deep traps located near the midgap. The steep decrease in Ea is thus a result from mixing of the two energy levels (Eg and midgap). Further, it is found that deep-trap-assisted tunneling under a high-field condition reduces Ea. The activation energy defined by the slope in the (log I) versus (1/T) plots is therefore not considered a direct indicator of real Et.

Representatively, memory has been limitedly used in advances, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Flash Memory. However, nowadays, memory is widely used in smartphones, automobiles, and the Internet of Things (IoT) in everyday electronic devices. Furthermore, there is currently a growing need for high-density memory in terms of size and energy efficiency due to increasing data and computation demands. Non-volatile Memories (NVMs) are promising candidates for achieving fast processing speeds, high data storage density, and energy efficiency because emerging NVMs (STT-MRAM, PCM, ReRAM) offer more of these advantages compared to conventional memory. Among NVMs, ReRAM boasts advantages such as non-volatility, fast write times, a larger resistance ratio (R-Ratio), and low power consumption. Despite the numerous advantages provided by RRAM, significant challenges still need to be addressed, such as resistance variations during fabrication and resistance drift during operation. This variation, which affects retention and the cycle, can lead to resistance degradation, resulting in a reduced the R-ratio (RHRS/RLRS) of ReRAM. Additionally, this resistance variation affects reference cells composed of ReRAM unit cells. Furthermore, resistance degradation can also affect the Bit-line voltage (VBL) during the read operation. Therefore, a low VBL is necessary to prevent this. However, maintaining a low VBL raises concerns about margin and delay. The proposed new sense amplifiers effectively address this variation. This first study proposes a reliable current sense amplifier assisted with dynamic reference (DR-CSA) to enhance sensing margin and robustness. The proposed sensing circuit detects a slight voltage change through capacitive coupling and adjusts the reference current based on the cell states (RHRS ,RLRS) to enhance the sensing margin. This second study introduces a novel time-based sensing (TBS) scheme for enhancing the speed and robustness during the operation and extends from single-level cells (SLC) to multi-level cells (MLC). In the proposed time-based sensing scheme, the bit line (BL) current is converted into a time delay based on cell states using the current-to-time converter (CTC). The resulting distinct time delays are compared to generate digital data. Additionally, The proposed sensing scheme executes sensing operations without using both a reference array and reference generator for reference current or reference voltage, which are required in a conventional current sense amplifier (CSA) or voltage sense amplifier (VSA). The last study introduces a novel hybrid cell-to-cell, referenceless sensing scheme. Since the proposed novel hybrid sensing scheme directly compares cell-to-cell, it requires no analog reference or generator, as is used in conventional voltage-mode schemes or current-mode schemes. Furthermore, the proposed scheme reads 2-bit data during the sensing process simultaneously and is compatible with two load modes: both voltage mode and current mode.

The new generations of dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM) technologies are contributing significantly toward increased system performance. Improvement in processing speed, however, can be hampered by inefficiency in both package performance and module-level interconnect. Furthermore, these high performance memory die have been designed with center bond pads rather than the peripheral bond format more common in earlier applications. The change in die layout, although challenging for traditional lead-frame package technology, has proved ideal for array packaging. The array format package with the die facing down furnishes a much shorter circuit path than lead-frame packaged die, minimizing the signal path between die and the printed circuit board (PCB) structure. For this reason, the developers of Rambus DRAM (RDRAM) and dual data rate (DDR) DRAM have found that array type packages enable optimized memory performance. To enable higher density memory, Tessera has developed a package stacking process the company has defined the “μZ™ Ball-Stack” package. The package technology is targeted for a variety of memory as well as multiple-function applications, however, to be widely adopted the ball-stack methodology must be subjected to extensive qualification and reliability testing.

The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state current and high switching ratio. The dual-gate TFET (DG-TFET) DRAM cell with the capacitorless structure has the superior performance-higher retention time (RT) and weak temperature dependence. But the performance of TFET DRAM cell is sensitive to programming condition. In this paper, the guideline of programming optimization is discussed in detail by using simulation tool—Silvaco Atlas. Both the writing and reading operations of DG-TFET DRAM depend on the band-to-band tunneling (BTBT). During the writing operation, the holes coming from BTBT governed by Gate2 are stored in potential well under Gate2. A small negative voltage is applied at Gate2 to retain holes for a long time during holding “1”. The BTBT governed by Gate1 mainly influences the reading current. Using the optimized programming condition, the DG-TFET DRAM obtains the higher current ratio of reading “1” to reading “0” (107) and RT of more than 2 s. The higher RT reduces the refresh rate and dynamic power consumption of DRAM.

Dynamic random access memory (DRAM) is facing the challenge of technology scaling. The de-creasing feature size makes it harder to make DRAM cells which can keep the current data-holding time. When DRAM cells cannot hold data for a long time, DRAM chips need a more frequent refreshing operation. There-fore, in the near future, time and energy cost on DRAM refreshing will be no longer trivial. In this paper, we propose DRAM Error Correction Pointer (ECP), an error-correction-manner framework, to reduce DRAM re-freshes without data loss. We exploit the non-uniform feature of DRAM cells with respect to the data retention time. Compared with the conventional refreshing mechanisms, which refresh DRAM chips by the retention time of the leakiest cells, we refresh the chips much fewer times, and treat the not-in-time refreshed cells as fault elements. We use the structure of ECP as a fault tolerant element. By recording the data which are supposed to be written into the leaky cells in our DRAM-ECP structures, DRAM-ECP can significantly decrease refreshing frequency. When these data are to be read out, DRAM-ECP retrieves the data stored in ECPs and covers them to the corresponding position in the data row. Our experiments show that DRAM-ECP can reduce over 70% refreshing operations than the current refreshing mechanism and also get significant energy saving.

In this paper, the dynamic random access memory (DRAM) cell technology is introduced and the important technological breakthroughs are reviewed. The criteria of DRAM memory cell design is discussed and the key fabrication technologies of 6F2 memory cell and stack capacitor DRAM cell are summarized. The technological evolution of array access transistor is also reviewed. The transistors with U-shaped transistor or FinFET and the fabrication process flow of 6F2 DRAM chip were discussed. Based upon the technical requirements for DRAM cell, the possible device technologies for the next generation DRAM cell was summarized. It is predicted that (1) U-shape channel transistor will be the mainstream technology for the future DRAM cell beyond 20 nm; (2) low k material will be required for decreasing the bitline parasitic capacitance; (3) sense-amplifier with better signal-noise margin will be required to ease the requirement of high aspect-ratio storage capacitance; (4) low power DRAM design will draw more attention, rather than increasing the storage capacity of DRAM.