Low-power process-variation tolerant arithmetic units using input-based elastic clocking

There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits remain in stand-by (or sleep) mode significantly longer than in active mode, their stand-by current, and not their active switching current, determines their battery life. Hence, stringent specifications are being placed on the stand-by (or leakage) current drawn by such devices. As the power supply voltage is reduced, the threshold voltage of transistors is scaled down to maintain a constant switching speed. Since reducing the threshold voltage increases the leakage of a device exponentially, leakage current has become a dominant factor in the design of VLSI circuits. In this paper, we describe a method that uses simultaneous dynamic voltage scaling (DVS) and adaptive body biasing (ABB) to reduce the total power consumption of a processor under dynamic computational workloads. Analytical models of the leakage current, dynamic power, and frequency as a function of supply voltage and body bias are derived and verified with SPICE simulation. Given these models, we show how to derive an analytical expression for the optimal trade-off between supply voltage and body bias, given a required clock frequency and duration of operation. The proposed method is then applied to a processor and is compared with DVS alone for workloads obtained using real-time monitoring of processor utilization for four typical applications.

In this paper, we propose a framework for low-energy digital signal processing (DSP) where the supply voltage is scaled beyond the critical voltage required to match the critical path delay to the throughput. This deliberate introduction of input-dependent errors leads to degradation in the algorithmic performance, which is compensated for via algorithmic noise-tolerance (ANT) schemes. The resulting setup comprised of the DSP architecture operating at sub-critical voltage and the error control scheme is referred to as soft DSP. It is shown that technology scaling renders the proposed scheme more effective as the delay penalty suffered due to voltage scaling reduces due to short channel effects. The effectiveness of the proposed scheme is also enhanced when arithmetic units with a higher delay-imbalance are employed. A prediction based error-control scheme is proposed to enhance the performance of the filtering algorithm in presence of errors due to soft computations. For a frequency selective filter, it is shown that the proposed scheme provides 60%-81% reduction in energy dissipation for filter bandwidths up to 0.5 /spl pi/ (where 2 /spl pi/ corresponds to the sampling frequency f/sub s/) over that achieved via conventional voltage scaling, with a maximum of 0.5 dB degradation in the output signal-to-noise ratio (SNR/sub o/). It is also shown that the proposed algorithmic noise-tolerance schemes can be used to improve the performance of DSP algorithms in presence of bit-error rates of up to 10/sup -3/ due to deep submicron (DSM) noise.

In this paper, we present an adaptive eight-transistor SRAM design that is capable of extending the operation of SRAM cells in the subthreshold region as well as maintaining high performance at the nominal supply voltages. The effective PMOS transistor size is dynamically adjusted according to the value of the supply voltage in order to sustain a balanced voltage transfer characteristics over the range of supply voltage operation. Simulation results demonstrate a power saving of up to 25% using our adaptive SRAM cell designed to maintain acceptable static noise margins under supply voltage in the range of 0.2 V to 1.2 V. The adaptive SRAM is very efficient for VLSI systems working under dynamic voltage scaling schemes, where the system is required to function at a variable supply voltage that extends to the subthreshold region of operation.

Starting from deep submicron technologies (< 0.13μm), and even stronger in nanometer technologies, static power consumption, due to leaky “off” transistors, is becoming a non-negligible contributor to the total power dissipation. Under this condition, the total power optimization problem changes considerably. The high parallelization approach commonly used today to increase performances, will soon result in power ineffcient designs. Indeed, the static power consumption of the large number of rarely used transistors will highly penalize the total power consumption. The purpose of this thesis is to investigate the influence of static power on the design methodologies for low power. In particular, the effects of architectural as well as technology modifications are explored. The use of technology as an optimization parameter has become possible in recent technologies. In fact, they offer different threshold voltages, each one showing a different trade-off between speed and leakage current. In this work, two different frameworks are considered. In the first one, both the supply voltage and the transistor threshold voltage are freely tunable parameters. This is the most general case and corresponds to the situation where the designer has the largest freedom. In the latter framework, we assume that the designer cannot change the supply voltage nor the transistor threshold voltage and they are hence considered constants. This case corresponds to the most common one, where the designer has a supply voltage and a technology type (and hence a threshold voltage) fixed by the application and by the devices the circuit has to interface. In both cases, lot of efforts have been put to the development of a handy way to rapidly estimate the total power consumption and consequently easily compare different architectural/technology variants at the early stages of development. Examples, based on multipliers, are used extensively in the whole thesis and, at the end, the presented theory is applied to a real circuit implemented in a 90nm technology by ST Microelectronics. Measurements show a very large variability of the static power over 16 dies manufactured on the same wafer. For instance, the highest static power consumption at nominal condition (Vdd=1V, f=62.5MHz) over the lowest one corresponds to more than a factor of 2.5. Measured data also report multipliers able to work at 210mV for a frequency of 1MHz!

The vast majority of the existing studies on GC-eDRAM focus on implementation in mature technology nodes (most often 0.18 μm CMOS and no lower than 65 nm CMOS) and at nominal supply voltages. This chapter studies the suitability of GC-eDRAM beyond these design spaces by analyzing aggressive technology scaling, down to 28 nm CMOS, and aggressive supply voltage scaling, all the way to the subthreshold (sub-VT) domain. First, the analytical retention time model developed in Chap. 3 is validated for a scaled 28 nm CMOS node. Second, a conventional 2T GC topology is optimized for sub-VT operation. Simulations show successful sub-VT operation for a 2T GC-eDRAM array in 0.18 μm CMOS. Furthermore, a 2T GC-eDRAM array implemented in a scaled 40 nm CMOS can be operated successfully down to the near-VT domain, while simultaneous aggressive technology and voltage scaling to the sub-VT domain are not recommended.

Low-power CMOS design has relied heavily on V DD scaling in the past to exploit the quadratic dependence of dynamic power and the exponential dependence of leakage power on voltage. Today, leading-edge low-voltage designs are pushing FET operation into the weak inversion and subthreshold regimes. Investigators around the world are reporting circuits at voltages between 180mV and 700mV that offer performance which could support a range of applications in wireless sensors, mobile phones, biomedical devices, and ultra-mobile PCs. However, these circuits are highly sensitive to variations in temperature and process. Ultra-low-voltage circuits will be increasingly challenging to design as feature sizes shrink. Current trends indicate nominal supply voltages are unlikely to be reduced much below 1V, transistor threshold voltages will likely remain between 0.3 and 0.4V to manage subthreshold leakage, and effects such as random- dopant fluctuation will increase the spread in transistor parameters, all of which create difficulties in designing robust circuits at low V DD . This Forum brings together leading experts to describe future challenges in ultra-low-voltage design, to explore ultra-low-voltage circuit techniques, and to stimulate thinking about prospects for future ultra-low-voltage high-volume products.

Shrinking feature sizes, reduced voltages, and higher transistor count of nano-scale silicon chips challenge designers in terms of performance, power consumption, and reliability. This paper investigates the effect of simultaneous use of dynamic voltage and frequency scaling (DVFS) and body biasing (BB) on power consumption, reliability, and performance. An analytical model of reliability as a function of body bias voltage, supply voltage, and frequency is proposed. We derive a three dimensional optimization problem by exploiting proposed reliability model in conjunction with power consumption and performance model. The resulting problem is solved using widely-used geometric optimization to identify optimal supply voltage and body bias voltage and then is validated using accurate simulation. Afterwards, it is demonstrated how joint energy-performance-reliability space optimization method can be used in an adaptive reliability-aware power management systems. Finally, we show that combined soft error aware BB and DVFS is capable of improving power consumption about 30% in comparison to reliability-aware DVFS only for the same level of reliability and performance constraints.

Energy consumption has become a major constraint in providing increased functionality for devices with small form factors. Dynamic voltage and frequency scaling has been identified as an effective approach for reducing the energy consumption of embedded systems. Earlier works on dynamic voltage scaling focused mainly on performing voltage scaling when the CPU is waiting for memory subsystem or concentrated chiefly on loop nests and/or subroutine calls having sufficient number of dynamic instructions. This paper concentrates on coarser program regions and for the first time uses program phase behavior for performing dynamic voltage scaling. Program phases are annotated at compile time with mode switch instructions. Further, we relate the Dynamic Voltage Scaling Problem to the Multiple Choice Knapsack Problem, and use well known heuristics to solve it efficiently. Also, we develop a simple integer linear program formulation for this problem. Experimental evaluation on a set of media applications reveal that our heuristic method obtains a 38% reduction in energy consumption on an average, with a performance degradation of 1% and upto 45% reduction in energy with a performance degradation of 5%. Further, the energy consumed by the heuristic solution is within 1% of the optimal solution obtained from the ILP approach.KeywordsExecution TimeSupply VoltageKnapsack ProblemBasic BlockProgram RegionThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

The implementation of a low-voltage zero-voltage-switching quasi-square-wave (ZVS-QSW) buck converter capable of meeting the future challenges of low-voltage VRMs is presented. By eliminating switching losses, high-efficiency operation at switching frequencies beyond 1 MHz is achieved. The design uses novel high-speed dead-time-locked-loops with fast dead-time error rejection to ensure zero-voltage-switching under dynamic loads and variable output conditions. The ZVS-QSW converter, which was implemented in a mixed-signal 0.18 m CMOS process, has a measured efficiency of 82% at 5 MHz with a 1.4 V output. The ZVS-QSW converter is intended to supply the next generation VLSI chips with a variable supply voltage for dynamic voltage scaling (DVS) applications. DVS refers to the real-time scaling of the supply voltage to the VLSI chip to minimize dynamic power consumption, while satisfying a variable target clock frequency. Several DVS strategies are examined, and it is shown that DVS can be applied to the ZVS-QSW converter using a dual-mode configuration. An experimental DVS test-bench was developed using a state-of-the-art Xilinx CPLD capable of operating from 1.35 V to 1.8 V. The PID controlled DVS system achieves the maximum V/sub DD/ transition in 22 /spl mu/s.

DDR4 SDRAM is expected to realize low power consumption and high bandwidth using a 1.2V nominal supply voltage and to be a cost-effective solution for various applications. In this paper, bank group architecture, internal reference voltage level (IVREF) and pre-emphasis to overcome conventional operating frequency range are presented. CS_n to command/address latency (CAL), data bus inversion (DBI) and ×4 half-page architecture are introduced to reduce current consumption. Cyclic redundancy check (CRC) and command and address (CA) parity are adopted to check transmission errors in high bandwidth. Also, read CRC with DBI is calculated in parallel to mitigate calculation time and area penalty. Consequently, our 2Gb DDR4 SDRAM achieves 2.4Gb/s data rate at 1.0V supply voltage.

Compiler-directed dynamic voltage scaling (DVS) is an effective low-power technique in real-time applications, where compiler inserts voltage scaling points in a real-time application, and supply voltage and clock frequency are adjusted to the relationship between the remaining time and remaining workload at each voltage scaling point. In this paper we present the analytical energy model of proportional dynamic voltage scaling in real-time applications. Using the analytical model, we theoretically prove the optimal configuration of voltage scaling points that minimizes energy consumption. Furthermore, in order to seek the optimal configuration taking into account voltage scaling overhead in the most frequent execution case, we propose a configuration methodology, where a profile-based method constructs the abstract execution pattern of an application, voltage scaling points are inserted into the abstract execution pattern by the optimal configuration without taking into account voltage scaling overhead, and then we can find the optimal configuration considering voltage scaling overhead by deleting some voltage scaling points from the execution pattern. Finally, the remaining points are inserted into the application by compiler. The simulation results show that, when taking into account voltage scaling overhead, the configuration methodology reduces energy consumption efficiently.KeywordsSupply VoltageClock FrequencyOptimal ConfigurationSlack TimeDynamic Voltage ScalingThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak performance is unnecessary. However, the achievable power saving by DVS alone is becoming limited as leakage power increases. In this paper, we show how the simultaneous use of adaptive body biasing (ABB) and DVS can be used to reduce power in high-performance processors. Analytical models of the leakage current, dynamic power, and frequency as functions of supply voltage and body bias are derived and verified with SPICE simulation. We then show how to determine the correct trade-off between supply voltage and body bias for a given clock frequency and duration of operation. The usefulness of our approach is evaluated on real workloads obtained using real-time monitoring of processor utilization for four applications. The results demonstrate that application of simultaneous DVS and ABB results in an average energy reduction of 48% over DVS alone.

In this paper, “tapered-Vth” buffers are explored as an approach to significantly improve the energy efficiency of traditional CMOS buffers. In this approach, the transistor threshold voltage is progressively increased throughout the buffer stages, in addition to the traditional transistor tapered sizing. Analysis shows that tapered-Vth buffers are able to significantly widen the range of energy-delay trade-offs achievable in real designs, thereby showing improved design flexibility compared to single-Vth buffers. In addition, tapered-Vth buffers are shown to offer an up to 3× energy reduction under a given performance constraint. A circuit-level optimization procedure including the leakage energy contribution is adopted to explore the entire energy-delay space, in contrast to previous analyses that targeted only a specific point. To this aim, an analytical framework to express the energy-delay trade-off of CMOS buffers is presented, based on the Logical Effort methodology. Simulations in a 45-nm CMOS technology are extensively performed to validate the approach in a case study (Word Lines buffers for memory arrays) and in a number of other design cases. Extensive simulations are performed to understand the limits of the proposed approach, as well as the impact of the activity rate, the supply voltage, and process variations.

The written-in errors in bit patterned media recording (BPMR) system cause the erroneous bits during the writing process leading to the performance degradation. In this work, we propose the pattern-dependent modified log-likelihood ratio (LLR) usage in low-density parity check (LDPC) decoder to reduce the written-in errors and also improve the write margin. Unlike the existing works, LLR computed based on the input data patterns is used at the LDPC decoder for the cascaded written-in error channel (WEC) with the additive white Gaussian noise (AWGN) channel. The proposed LDPC decoder outperforms the one with conventional LLR in terms of both the write margin, when the SNR is fixed at 5.5 dB, and the performance of LDPC decoder. The SNR gain is about 0.2 dB at the BER of 10- 6.

Compiler-directed dynamic voltage scaling (DVS) is one of the effective low-power techniques for real-time applications. Using the technique, compiler inserts voltage scaling points into a real-time application, and supply voltage and clock frequency are adjusted to the relationship between the remaining time and the remaining workload at each voltage scaling point. In this paper, based on the WCET (the worst case execution time) analysis tool HEPTANE and the performance/power simulator Sim-Panalyzer, we present a DVS-enabled simulation environment RTLPower (Real-Time Low Power), which integrates static WCET estimation, performance/power simulation, automatically inserting the DVS code into a real-time application, and profile-guided energy optimization. By simulations of some benchmark applications, we prove that the DVS technique and the profile-guided optimization technique significantly reduce energy consumption.