Low Power Synthesis and Validation of an Embedded Multiplier for FPGA Based Wireless Communication Systems

The potential of FPGAs as accelerators for high-performance computing applications is very large, but many factors are involved in their performance. The design for FPGAs and the selection of the proper optimizations when mapping computations to FPGAs lead to prohibitively long developing time. Alternatives are the high-level synthesis (HLS) tools, which promise a fast design space exploration due to design at high-level or analytical performance models which provide realistic performance expectations, potential impediments to performance, and optimization guidelines. In this paper we propose the combination of both, in order to construct a performance model for FPGAs which is able to visually condense all the helpful information for the designer. Our proposed model extends the roofline model, by considering the resource consumption and the parameters used in the HLS tools, to maximize the performance and the resource utilization within the area of the FPGA. The proposed model is applied to optimize the design exploration of a class of window-based image processing applications using two different HLS tools. The results show the accuracy of the model as well as its flexibility to be combined with any HLS tool.

There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area in contemporary SoC designs and are the main contributors to system leakage power dissipation. Existing models for leakage power estimation in array structures typically use coefficients derived from elaborate SPICE simulations. However, these methodologies are not applicable to array designs in a newer technology, that require power estimates early in the design cycle. In this paper, we propose analytical models for array structures that are based only on high level design parameters. Assuming typical circuit implementation styles, we identify the transistors that contribute to the leakage power in each array sub-circuit and develop models as a function of the operation (read/write/idle) on the array and organizational parameters of the array. The developed models are validated by comparing their estimates against the leakage power measured using SPICE simulations on industrial array designs belonging to the e5001 processor core. The comparison shows that the models are accurate with an error margin of less than 21.5% and thus can be used in high-level power-performance exploration. Interestingly, in array designs with dual threshold voltage technology, we observed that contrary to the general expectation, the array memory core contributes to just 9% and the address decoder contributes to as much as 62% of the total leakage power.

A flip-flop using a combination of thin and thick gate transistors combines high performance and low standby power. Setup and hold times are controlled by the master latch implemented in high performance transistors, while a thick gate slave latch provides state retention at low standby power when the high performance circuit power supply is gated off. The design has reduced circuit and power-down control complexity compared to previously described circuits using thick gate shadow latches for low standby power state storage. Measured test chip results on a foundry 130 nm process prove the viability of the design. The thick gate shadow latches are shown to have good retention capability at low supply voltages, suggesting that reduced shadow latch supply voltage during standby will be effective at mitigating the drain to bulk leakage components that are increasingly limiting for low power standby modes.

Dynamic power management at the lowest design level of electronic hardware, i.e. at the device or transistor level, is still a novelty. Instead, energy saving is usually achieved at the circuit level by switching off high performance components and activating low leakage transistors in the current paths. We discuss here performance projections of field-effect transistors providing multiple power modes. A multi-mode (mm) FET can be configured from GHz performance to ultralow leakage by adjusting the charge injection into the transistor channel between thermionic and band-to-band tunnel injection. Nanodevices with ultrathin doping-free channels are the enabler of this novel device concept that requires excellent electrostatic control of the charge type and density. Moreover, nanomaterials with charge carriers of low effective mass will improve the mode tuning of mmFETs. TCAD simulations show that the device current can be switched through nine orders of magnitude at a supply voltage of . The mmFET can also operate in a low dynamic power mode with reduced drive currents but delay times that still allow sub-MHz operation. These properties make mmFETs a promising technology for low power circuitry supplied only by energy harvesters. The possibility to further decrease the supply voltage by integrating a ferroelectric layer in the capacitor stack is also addressed.

Over the last fifty years, societies across the world have experienced multiple periods of energy insufficiency with the most recent one being the 2022 global energy crisis. In addition, the electric power industry has been experiencing a steady increase in electricity consumption since the second industrial revolution because of the widespread usage of electrical appliances and devices. Newer devices are equipped with sensors and actuators, they can collect a large amount of data that could help in power management. However, current energy management approaches are mostly applied to limited types of devices in specific domains and are difficult to implement in other scenarios. They fail when it comes to their level of autonomy, flexibility, and genericity. To address these shortcomings, we present, in this paper, an automated energy management approach for connected environments based on generating power estimation models, representing a formal description of energy-related knowledge, and using reinforcement learning (RL) techniques to accomplish energy-efficient actions. The architecture of this approach is based on three main components: power estimation models, knowledge base, and intelligence module. Furthermore, we develop algorithms that exploit knowledge from both the power estimator and the ontology, to generate the corresponding RL agent and environment. We also present different reward functions based on user preferences and power consumption. We illustrate our proposal in the smart home domain. An implementation of the approach is developed and two validation experiments are conducted. Both case studies are deployed in the context of smart homes: (a) a living room with a variety of devices and (b) a smart home with a heating system. The obtained results show that our approach performs well given the low convergence period, the high level of user preferences satisfaction, and the significant decrease in energy consumption.

Dual-Tone Multi-frequency (DTMF) is the Standardized term in the telecom industry, where if anyone press a key two tones are generated simultaneously. The DTMF tone detection is an important block in several embedded applications, which works for low-power devices. The DTMF detection using high-end FPGA is carried out by using the Goertzel algorithm and further the design is optimized by using the resource-sharing approach. The resource-sharing approach uses less area, less delay, and low power. Vey few multiplexers, adders are used as compared to the conventional approach of DTMF detection. All the timing diagrams are analyzed using the ModelSim simulation software. Pre-synthesis and post-synthesis are carried out using the XILINX Vivado. Virtex-5 FPGA device is used to check the functionality of the hardware.

PLX is a concise instruction set architecture (ISA) that combines the most useful features from previous generations of multimedia instruction sets with newer ISA features for high-performance, low-cost multimedia information processing. Unlike previous multimedia instruction sets, PLX is not added onto a base processor ISA, but designed from the beginning as a standalone processor architecture optimized for media processing. Its design goals are high performance multimedia processing, general-purpose programmability to support an ever-growing range of applications, simplicity for constrained environments where low power and low cost are paramount, and scalability for higher performance in less constrained multimedia systems. Another design goal of PLX is to facilitate exploration and evaluation of novel techniques in instruction set architecture, microarchitecture, arithmetic, VLSI implementations, compiler optimizations, and parallel algorithm design for new computing paradigms. Key characteristics of PLX are a fully subword-parallel architecture with novel features like wordsize scalability from 32-bit to 128-bit words, a new definition of predication, and an innovative set of subword permutation instructions. We demonstrate the use and high performance of PLX on some frequently-used code kernels selected from image, video, and graphics processing applications: discrete cosine transform, pixel padding, clip test, and median filter. Our results show that a 64-bit PLX processor achieves significant speedups over a basic 64-bit RISC processor and over IA-32 processors with MMX and SSE multimedia extensions. Using PLX's wordsize scalability feature, PLX-128 often provides an additional 2× speedup over PLX-64 in a cost-effective way. Superscalar or VLIW (Very Long Instruction Word) PLX implementations can also add additional performance through inter-instruction, rather than intra-instruction parallelism. We also describe the PLX testbed and its software tools for architecture and related research.

The design of efficient multiprocessor systems on chip (MPSoC) is a daunting challenge. This challenge is driven by the increasing demand in achieving high performance, low power, and reconfigurable applications onto the same platform. As a consequence, there is an emerging need for fast, and efficient design space exploration, while providing abstract models for a wide range of applications, and types of processing units (PUs). Therefore, this paper proposes a framework for a fast MPSoC generation with joint task and core mapping with the objective of minimizing the average power consumption. The proposed framework considers the static, dynamic, reconfiguration and communication power components. A tool for high level MPSoC task and core mapping (MPMAP) is built based on the proposed framework. MPMAP provides a flexible XML interface that provides a high level description of the different PU architectures, and different applications scenarios. Additionally, the paper presents a case study of real-life applications that can be adopted in future heterogeneous wireless systems.

In this paper we propose a methodology that takes into account bit-width to optimize area and power consumption of hardware architectures provided by high level synthesis tools. The methodology is based on a bit-width analysis using information that comes from the designer. This bit-width information is propagated through a graph which models the application. The resulting annotated graph enables datapath structure optimizations for high level synthesis without increasing dramatically its processing time (complexity: O(n)). The methodology was applied to several signal and image processing applications. Our results demonstrate the effectiveness of the approach. It can be also applied in a more general design context for sizing the data of an application knowing the input data formats and their potential correlation.

Embedded systems used in real-time applications require low power, less area and high computation speed. For digital signal processing, image processing and communication applications, data are often received at a continuously high rate. The type of necessary arithmetic functions and matrix operations may vary greatly among different applications. The RTL-based design and verification of one or more of these functions could be time-consuming. Some High Level Synthesis tools reduce this design and verification time but may not be optimal or suitable for low power applications. The design tool proposed in this paper can improve the design time and reduce the verification process. The design tool offers a fast design and verification platform for important matrix operations. These operations range from simple addition to more complex matrix operations such as LU and QR factorizations. The proposed platform can improve design time by reducing verification cycle. This tool generates Verilog code and its testbench that can be realized in FPGA and VLSI systems. The designed system uses MATLAB-based verification and reporting.

Accurate estimation of power plays an important role in designing and monitoring a bifacial PV (BFPV) system. The way to obtain BFPV power by PVlib, as the common simulation approach, is identical to monofacial PV (MFPV), where the bifaciality concept is utilized as a simplifying assumption, and an effective irradiance is employed to consider both front and back radiation together. In addition, during the recent years, a wide range of data-driven approaches, including semi-empirical models, digital twins, and machine learning techniques such as artificial neural networks and ensemble methods, have been explored for BFPV power estimation. While these methods have shown promising accuracy, most of them still rely on rear irradiance measurements, albedo assumptions, or extensive input parameters, which limits their generalizability in real-world BFPV scenarios. Considering the mentioned points, we presented a novel physical data-driven model for estimation of BFPV power output (called the DBPG2 model). The big advantage of DBPG2 model compared to models in the literature is that it does not need rear tilted irradiance (RTI) or albedo and module bifaciality coefficient. The DBPG2 model is trained and tested for a variety of BFPV systems in different parts of the world, with various configurations and albedo conditions. It includes: (1) A fixed-tilt (FT) system at Technical University of Denmark (DTU), (2) A single axis tracking (SAT) system at DTU, (3) A vertically mounted system in Turku, Finland, (4) One row from Bifacial Experimental Single-axis Tracking (BEST) system of National Renewable Energy Lab (NREL) in the Colorado, the USA, and (5 and 6) SAT systems with black and white ground in EURAC Research, Bolzano, Italy. They are called DTU FT, DTU SAT, Turku VER, NREL BEST SAT, EURAC SAT Black Ground, and EURAC SAT White Ground, respectively. According to the results, due to high changes in the albedo over time and small size of the string, the DBPG2 model has a higher error than PVlib for Turku VER (2.47% vs. 1.60%). However, it outperforms PVlib in all other case studies. The normalized root mean square error (NRMSE) for the DBPG2 model and PVlib are: 0.61% and 0.95% (DTU FT), 0.61% and 0.97% (DTU SAT), 1.88% and 3.01% (NREL BEST SAT), 0.77% and 2.07% (EURAC SAT Black Ground), and 1.44% and 3.85% (EURAC SAT White Ground). The findings show a more significant improvement of the DBPG2 model in comparison to PVlib for high albedo and single axis tracker, which is usually the preferred working condition of BFPV systems. • A novel physical data-driven model, called DBPG2, is proposed to estimate bifacial PV (BFPV) power. • DBPG2 model estimates BFPV power without rear tilted irradiance or albedo data. • DBPG2 model outperforms PVlib for various examined cases worldwide with different configurations. • Not only power, but also yield is estimated more accurately by DBPG2 model than PVlib. • DBPG2 model has more improvement for cases with higher albedo and single-axis tracker.

Recent developments in High Level Synthesis tools have attracted software programmers to accelerate their high-performance computing applications on FPGAs. Even though it has been shown that FPGAs can compete with GPUs in terms of performance for stencil computation, most previous work achieve this by avoiding spatial blocking and restricting input dimensions relative to FPGA on-chip memory. In this work we create a stencil accelerator using Intel FPGA SDK for OpenCL that achieves high performance without having such restrictions. We combine spatial and temporal blocking to avoid input size restrictions, and employ multiple FPGA-specific optimizations to tackle issues arisen from the added design complexity. Accelerator parameter tuning is guided by our performance model, which we also use to project performance for the upcoming Intel Stratix 10 devices. On an Arria 10 GX 1150 device, our accelerator can reach up to 760 and 375 GFLOP/s of compute performance, for 2D and 3D stencils, respectively, which rivals the performance of a highly-optimized GPU implementation. Furthermore, we estimate that the upcoming Stratix 10 devices can achieve a performance of up to 3.5 TFLOP/s and 1.6 TFLOP/s for 2D and 3D stencil computation, respectively.

Several studies have reported changes in spontaneous brain rhythms that could be used as clinical biomarkers or in the evaluation of neuropsychological and drug treatments in longitudinal studies using magnetoencephalography (MEG). There is an increasing necessity to use these measures in early diagnosis and pathology progression; however, there is a lack of studies addressing how reliable they are. Here, we provide the first test-retest reliability estimate of MEG power in resting-state at sensor and source space. In this study, we recorded 3 sessions of resting-state MEG activity from 24 healthy subjects with an interval of a week between each session. Power values were estimated at sensor and source space with beamforming for classical frequency bands: delta (2-4 Hz), theta (4-8 Hz), alpha (8-13 Hz), low beta (13-20 Hz), high beta (20-30 Hz), and gamma (30-45 Hz). Then, test-retest reliability was evaluated using the intraclass correlation coefficient (ICC). We also evaluated the relation between source power and the within-subject variability. In general, ICC of theta, alpha, and low beta power was fairly high (ICC > 0.6) while in delta and gamma power was lower. In source space, fronto-posterior alpha, frontal beta, and medial temporal theta showed the most reliable profiles. Signal-to-noise ratio could be partially responsible for reliability as low signal intensity resulted in high within-subject variability, but also the inherent nature of some brain rhythms in resting-state might be driving these reliability patterns. In conclusion, our results described the reliability of MEG power estimates in each frequency band, which could be considered in disease characterization or clinical trials.

The demand for high-performance chip-scale lasers has driven rapid growth in integrated photonics. The creation of such low-noise laser sources is critical for emerging on-chip applications, ranging from coherent optical communications, photonic microwave oscillators remote sensing and optical rotational sensors. While Brillouin lasers are a promising solution to these challenges, new strategies are needed to create robust, compact, low power and low cost Brillouin laser technologies through wafer-scale integration. To date, chip-scale Brillouin lasers have remained elusive due to the difficulties in realization of these lasers on a commercial integration platform. In this paper, we demonstrate, for the first time, monolithically integrated Brillouin lasers using a wafer-scale process based on an ultra-low loss Si3N4/SiO2 waveguide platform. Cascading of stimulated Brillouin lasing to 10 Stokes orders was observed in an integrated bus-coupled resonator with a loaded Q factor exceeding 28 million. We experimentally quantify the laser performance, including threshold, slope efficiency and cascading dynamics, and compare the results with theory. The large mode volume integrated resonator and gain medium supports a TE-only resonance and unique 2.72 GHz free spectral range, essential for high performance integrated Brillouin lasing. The laser is based on a non-acoustic guiding design that supplies a broad Brillouin gain bandwidth. Characteristics for high performance lasing are demonstrated due to large intra-cavity optical power and low lasing threshold power. Consistent laser performance is reported for multiple chips across multiple wafers. This design lends itself to wafer-scale integration of practical high-yield, highly coherent Brillouin lasers on a chip.

A new high-speed domino circuit, called HS-Domino has been developed. HS-Domino resolves the tradeoff between performance and reliability in conventional CD-domino logic while dissipating low dynamic power with minimal area overhead. HS-Domino, therefore, extends domino's operation in the deep submicron regime. A multithreshold implementation of HS-Domino is also devised to achieve substantially low leakage values during standby, while maintaining high performance and low power during the active mode. Furthermore, the generic multithreshold scheme is applied to differential cascode voltage switch (DDCVS) logic.