LOW POWER SYSTEM DESIGN BY COMBINING SOFTWARE PREFETCHING AND DYNAMIC VOLTAGE SCALING

Performance-enhancement techniques improve CPU speed, but at higher cost to other valuable system resources such as power and energy. We study this trade-off using software prefetching as the system performance-enhancement technique. We first demonstrate software prefetching provides an average 36% performance boost with 8% more energy consumption and 69% higher power on six memory-intensive benchmarks. However, when we combine prefetching with a (unrealistic) static voltage scaling technique, the performance gain afforded by prefetching can be traded off for savings in power/energy consumption. In particular, we observe a 48% energy saving when we slow down the system with prefetching so as to match the performance of the system without prefetching. This suggests a promising approach to build low power systems by transforming traditional performance-enhancement techniques into low power methods. We thus propose a real time dynamic voltage scaling (DVS) algorithm that monitors a system's performance and adapts the voltage level accordingly while maintaining the observed system performance. Our dynamic DVS algorithm achieves a 38% energy saving without any performance loss on our benchmark suite.

During the last several years, dynamic voltage scaling (DVS) algorithms are being used for energy consumption on real, fully functional battery supplied devices, adjusting the clock speed and supply voltage dynamically. Most DVS algorithms are investigated in interval-based and task-based strategies. Task-based algorithms consider task information, especially task deadline, on deciding what speed to choose at any given time. Interval-based algorithms predict the CPU speed of the upcoming interval based on observations of the CPU utilization of previous intervals, and then set the speed for that interval based on this prediction. Most DVS algorithms have only been tested in simulation environments. In this paper, those interval-based DVS algorithms are modified with different parameters on different workloads, and evaluated to know which one saves the most energy while not degrading computer performance.

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> The high complexity and time-varying workload of emerging multimedia applications poses a major challenge for dynamic voltage scaling (DVS) algorithms. Although many DVS algorithms have been proposed for real-time applications, an efficient method for evaluating the optimality of such DVS algorithms for multimedia applications does not yet exist. In this paper, we propose the first offline linear programming (LP) method to determine the minimum energy consumption for processing multimedia tasks under stringent delay deadlines. On the basis of the obtained energy lower bound, we evaluate the optimality of various existing DVS algorithms. Furthermore, we extend the LP formulation in order to construct an online DVS algorithm for real-time multimedia processing based on robust sequential linear programming. Simulation results obtained by decoding a wide range of video sequences show that, on average, our online algorithm provides a scheduling solution that requires less than 0.3% more energy than the optimal lower bound with only 0.03% miss rate. In comparison, a very recent algorithm consumes approximately 4% more energy than the optimal lower bound at the same miss rate. </para>

Dynamic Voltage Scaling (DVS), which adjusts the clock speed and supply voltage dynamically, is an effective technique in reducing the energy consumption of embedded real-time systems. Unlike dynamic-priority real-time scheduling for which highly effective DVS algorithms are available, existing fixed-priority DVS algorithms are less effective in energy efficiency because they are based on inefficient slack estimation methods. This paper describes an efficient on-line slack estimation heuristic for the rate-monotonic (RM) scheduling. The proposed heuristic estimates the slack times using the short term work-demand analysis. The DVS algorithm,based on-the proposed heuristic is also presented. Experimental results show that the proposed DVS algorithm reduces the energy consumption by 25/spl sim/42% over the existing rate-monotonic DVS algorithms.

Along with the prevailing of mobile devices, the demand for efficient power consumption has become one of the major issues in designing embedded system. Dynamic Voltage Scaling (DVS) is a technique that can reduce energy consumption by changing the processor voltage levels dynamically. Fixed Priority with Preemption Threshold (FPPT) scheduling is a scheduling policy that includes preemptive and non-preemptive aspect of scheduling policy. In this paper, an efficient universal fixed priority DVS algorithm (FPPT-DVS) will be presented. This algorithm has the advantage of both Fixed Priority Preemptive (FPP) DVS scheduling and Fixed Priority Non-Preemptive (FPNP) DVS scheduling. FPPT-DVS algorithm also combines the on-line DVS and off-line DVS together. Experimental results show that the proposed FPPT-DVS algorithm can save up to 20% energy over the existing DVS algorithms.

A new dynamic voltage scaling (DVS) approach to schedule sporadic, hard real-time tasks with shared resource in a power saving way is proposed. Although DVS algorithms have been recognized as a feasible solution to save energy, the scheduling of such tasks has not been fully explored. Thus, in the paper, the problem of power-saving scheduling for sporadic tasks that share a set of serially reusable, single unit software resources is investigated. To evaluate the performance of DVSSR, a real application, Robotic Highway Safety Marker (RSM), is employed. In this application, DVSSR and other DVS algorithms are simulated and compared. Simulation results show that DVSSR offers reasonable trade-off between cost and power savings. In RSM application, DVSSR achieves 92.03% average power savings while comparing with the classic DVS. Keywords: hard real-time and sporadic task, resource-sharing, task scheduling, dynamic voltage scaling, power savings

For real time applications, time slacks of a preliminary task schedule may be exploited to conserve energy. This can be accomplished by leveraging the dynamic voltage scaling (DVS) technique to slow down clock frequency of certain cores as long as the deadline is met. In this chapter, the task of fine-tuning an existing task assignment and schedule and using DVS to lower the overall energy consumption is formulated as a graph-theoretic maximum weight clique (MWC) problem. An efficient heuristic algorithm is proposed to systematically solve this problem. A unique feature of our approach is concurrently applying DVS to slow down the execution of multiple tasks to achieve better energy savings. Extensive simulations are performed to compare this proposed algorithm against leading energy-aware task scheduling algorithm and DVS algorithm. Our algorithm exhibits 22% more energy savings than the Energy Aware Scheduling (EAS) algorithm. As for energy saving in DVS process, our MWC-based method provides a 97% saving improvement over the PV-DVS algorithm.

In recent years, there has been a rapid and wide spread of non-traditional computing platforms, especially mobile and portable computing devices. As applications become increasingly sophisticated and processing power increases, the most serious limitation on these devices is the available battery life. Dynamic Voltage Scaling (DVS) has been a key technique in exploiting the hardware characteristics of processors to reduce energy dissipation by lowering the supply voltage and operating frequency. The DVS algorithms are shown to be able to make dramatic energy savings while providing the necessary peak computation power in general-purpose systems. However, for a large class of applications in embedded real-time systems like cellular phones and camcorders, the variable operating frequency interferes with their deadline guarantee mechanisms, and DVS in this context, despite its growing importance, is largely overlooked/under-developed. To provide real-time guarantees, DVS must consider deadlines and periodicity of real-time tasks, requiring integration with the real-time scheduler. In this paper, we present a class of novel algorithms called real-time DVS (RT-DVS) that modify the OS's real-time scheduler and task management service to provide significant energy savings while maintaining real-time deadline guarantees. We show through simulations and a working prototype implementation that these RT-DVS algorithms closely approach the theoretical lower bound on energy consumption, and can easily reduce energy consumption 20% to 40% in an embedded real-time system.

Modern real-time embedded systems have increasingly penetrated our daily life and are also often constrained in terms of temperature and energy. In this paper, a thesis is defended that from a real-time systems perspective, thermally constrained dynamic power management approaches behave very similar to idealised dynamic voltage and frequency scaling. Hence, existing dynamic voltage and frequency scaling solutions proposed for periodic/sporadic task models can be applied to thermally constrained dynamic power management systems with moderate effort. This work presents the similarities along with the distinctive elements between two approaches. Within the case study, the porting of a dynamic voltage and frequency scaling algorithm of the literature to thermally constrained dynamic power management system is demonstrated.

Slack computation for DVS algorithms in fixed-priority real-time systems using fluid slack analysis

Dynamic voltage scaling (DVS) is a powerful technique to reduce power dissipation in embedded systems. Some efficient DVS algorithms have been recently proposed for the energy reduction in distributed system. However, they achieve the energy savings solely by scaling the system task with respect to the timing constraints, while neglecting that power varies among, the tasks executed by DVS processing elements (DVS-PEs). In this paper we investigate the problem of considering DVS-PE power variations dependent on the executed tasks, during the synthesis of distributed embedded systems and its impact on the energy savings. Unlike previous approaches, which minimise the energy consumption by exploiting the available slack time without considering the PE power profiles, a new and fast heuristic for the voltage scaling problem is proposed, which improves the voltage selection for each task dependent on the individual power dissipation caused by that task. Experimental results show that energy reductions with up to 80.7% are achieved by integrating the proposed DVS algorithm, which considers the PE power profiles, into the co-synthesis of distributed systems.

Recently, a single chip multiprocessor (CMP) is becoming an attractive architecture for improving throughput of program execution. In CMPs, multiple processor cores share several hardware resources such as cache memory and memory bus. Therefore, the resource contention significantly degrades performance of each thread and also loses fairness between threads. In this paper, we propose a Dynamic Frequency and Voltage Scaling (DVFS) algorithm for improving total instruction throughput, fairness, and energy efficiency of CMPs. The proposed technique periodically observes the utilization ratio of shared resources and controls the frequency and the voltage of each processor core individually to balance the ratio between threads. We evaluate our technique and the evaluation results show that fairness between threads are greatly improved by the technique. Moreover, the total instruction throughput increases in many cases while reducing energy consumption.

Dynamic voltage and frequency scaling (DVFS) algorithms are widely used power management techniques which enable the optimization of system-level power dissipation, energy consumption and operation performance. One cost-effective hardware-enabling platform to implement the DVFS is through single-inductor multiple-output (SIMO) DC-DC converters. However, the major drawback with such converters is cross regulation, which leads to undesired supply voltage variations. These variations have significant impact on modern VLSI applications, from the circuit to the system level. Based on these challenges, this paper presents a cross-layered design of two SIMO DC-DC converters with an adaptive freewheel switching technique. The proposed converters are able to minimize cross regulation by adaptively adjusting the freewheel switching durations and currents. This also increases the efficiency of the SIMO converters, by reducing the conduction losses due to the lossy freewheel switch. To verify the cross regulation performance of the SIMO converters, its influence on clock frequencies generated by a ring oscillator is investigated. By simulating various load transient conditions, it is shown that the SIMO converters are able to significantly minimize frequency variations. The operation of the converters is verified through transistor-based HSPICE simulation results, with a 130-nm CMOS process. The SIMO converter with the digital-based adaptive freewheel switching controller achieves a maximum efficiency of 93.2%, while the analog counterpart achieves a maximum efficiency of 93.4%. For a load change from 200 mA to 40 mA, the proposed technique reduces the conduction losses during the freewheel switching duration by 99.96%, compared with traditional methods.

Traditional dynamic voltage scaling algorithms periodically monitor CPU utilization and adapt its operating frequency to the upcoming performance requirement for CPU power management. Predicting CPU utilization is usually conducted by estimating upcoming performance requirement. In order for dynamic voltage scaling algorithms to be effective, the prediction accuracy of CPU utilization must be high. This paper proposes a power management algorithm that improves accuracy of predicting future CPU utilization using process state information. Experiments show that the proposed algorithm reduces power consumption by 11%–57% without any performance degradation.

In this paper, we present a new methodology for managing power consumption of networks-on-chips (NOCs). A power management problem is formulated for the first time using closed-loop control concepts. We introduce an estimator and a controller that implement our power management methodology. The estimator is capable of very fast and accurate tracking of changes in the system parameters. Parameters estimated are used to form the system model. Our system model combines node and network centric power management decisions. Node centric power management assumes no a priori knowledge of requests coming in from outside the core. Thus, it implements a more traditional dynamic voltage scaling and power management control algorithms. Network-centric power management utilizes interaction with the other system cores regarding the power and the quality of service (QoS) needs. The overall system model is based on Renewal theory and, thus, guarantees globally optimal results. We introduce a fast optimization method that runs multiple orders of magnitude faster than the previous optimization approaches while still having the same accuracy in obtaining the power management control. Finally, our controller implements the results of optimization in either hardware or software. The new methodology for power management of NOCs is tested on a system consisting of four satellite units, each implementing an estimator and a controller capable of both node and network centric power management. Our results show large savings in power with good QoS.