<title>Forward error-correcting code for gigabit fiber optic links</title>

As the size of on-chip SRAM caches is increasing rapidly and the physical dimension of the SRAM devices is decreasing, reliability of caches is becoming a growing concern. This is because with increased size of caches, the likelihood of radiation-induced soft faults also increases. As a result, information redundancy in the form of Error Correcting Codes (ECC) is becoming extremely important, especially to protect the larger sized last level caches (LLCs). In typical ECCs, extra redundancy bits are added to every row to detect and correct errors. There is additional encoding (while writing data) and decoding (while reading data) procedures required as well. In caches, these additional area, power and latency overheads need to be minimized as much as possible. To address this problem, we present in this paper Parity++: a novel unequal message protection scheme for last level caches that preferentially provides stronger error protection to certain "special messages". This protection scheme provides Single Error Detection (SED) for all messages and Single Error Correction (SEC) for a subset of messages. Thus, it is stronger than just a basic SED parity and has much lower parity storage overhead (4X lower for a 64-bit memory) and lower error detection energy than a traditional Single Error Correcting, Double Error Detecting (SECDED) code. We also evaluate Parity++ with a memory speculation procedure that can be used with any ECC scheme to hide the decoding latency while reading messages when there are no errors.

Circuit techniques for reducing the minimum supply voltage (V MIN ) of last-level and intermediate static random-access memory (SRAM) caches enhance processor energy efficiency. For the first time at a 16nm technology node, projections of a high-density 6-transistor SRAM bit cell indicate that the VMIN of a 4Mb or larger cache exceeds the maximum supply voltage (V MAX ) for reliability. Thus, circuit techniques for cache VMIN reduction are transitioning from an energy-efficient solution to a requirement for cache functionality. Traditionally, error-correcting codes (ECC) such as single-error correction, double-error detection (SECDED) aim to protect the cache operation from radiation-induced soft errors. Moreover, during the qualification of a system-on-chip (SoC) processor, test engineers monitor the rate of correctable cache errors from SECDED for observing the on-die interactions between integrated components (e.g., CPU, GPU, DSP, etc.). This presentation highlights the opportunity to exploit ECC for reducing the cache V MIN while simultaneously providing coverage for radiation-induced soft errors. Silicon test-chip measurements from a 7Mb data cache in a 20nm technology demonstrate a V MIN reduction of 19% from SECDED. In addition, silicon measurements provide a salient insight in that only 0.12% of the cache words contain an error when operating at the cache V MIN with SECDED. Therefore, SECDED improves V MIN by 19% while maintaining 99.88% coverage for radiation-induced soft errors. In applying SECDED for a lower cache VMIN, the rate of correctable errors exponentially increases, thus eliminating a useful metric for on-die observability. The presentation concludes by offering alternative solutions for on-die observability.

Radiation-induced soft errors are a major reliability concern for memories. To ensure that memory contents are not corrupted, single error correction double error detection (SEC-DED) codes are commonly used, however, in advanced technology nodes, soft errors frequently affect more than one memory bit. Since SEC-DED codes cannot correct multiple errors, they are often combined with interleaving. Interleaving, however, impacts memory design and performance and cannot always be used in small memories. This limitation has spurred interest in codes that can correct adjacent bit errors. In particular, several SEC-DED double adjacent error correction (SEC-DED-DAEC) codes have recently been proposed. Implementing DAEC has a cost as it impacts the decoder complexity and delay. Another issue is that most of the new SEC-DED-DAEC codes miscorrect some double nonadjacent bit errors. In this brief, a new class of SEC-DED-DAEC codes is derived from orthogonal latin squares codes. The new codes significantly reduce the decoding complexity and delay. In addition, the codes do not miscorrect any double nonadjacent bit errors. The main disadvantage of the new codes is that they require a larger number of parity check bits. Therefore, they can be useful when decoding delay or complexity is critical or when miscorrection of double nonadjacent bit errors is not acceptable. The proposed codes have been implemented in Hardware Description Language and compared with some of the existing SEC-DED-DAEC codes. The results confirm the reduction in decoder delay.

Single bit errors occur more frequently in memory elements. So for the avoidance of these single bit errors the Hamming code technique was recognized as the best among all other coding techniques. The most effective coding technique was Hamming [16, 11, 5] <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> which results in single error detection and correction as well as double adjacent error detection and correction. In this paper, a method to design SEC-DAEC codes with optimized decoding is presented and evaluated. Extended Hamming code is developed by adding an extra parity bit. The implementation is evaluated and compared by its application in an audio signal authentication in matlab with introduced errors The evaluations show there is a slight increase in area, power and delay of the decoder.

Phase-change memory (PCM) and resistive memory (RRAM) are promising alternatives to traditional memory technologies. However, both PCM and RRAM suffer from limited write endurance. Wear-leveling (WL) techniques are essential to extend the lifetime of these memories before experiencing endurance faults. Beyond the additional usage afforded by WL, row-sparing and focused error correction can extend the lifetime further after wear faults appear. Unfortunately, the need for extended WL techniques continues to become more pressing as scaling exacerbates process variation. Similarly, scaling causes challenges such as more severe noise and crosstalk to traditional DRAM.In this paper, we propose novel fault-aware WL schemes to allocate write frequencies according to the strength of the rows and handle the imbalance of writes in columns. We use runtime detection schemes to identify weak rows and protect them prior to wear out. In particular, row-level WL, aka RETROFIT, leverages the spare rows provided for redundancy to be used strategically to guard against early cell wear out. RETROFIT is compatible with error correction schemes that guarantee to mitigate hard faults and error-correcting codes (ECC). Rather than discard retired rows, when any spare row completely replaces a retired row, we retarget the retired row to assist with column sparing. It becomes a group of Page Protecting Pointers (PPPs), which utilizes otherwise discarded error correction potential to further enhance the leveling ability of RETROFIT. To relieve column-level imbalance, we apply idle error correction bits before they are used to reduce average bit flips. The evaluation demonstrates that RETROFIT and enhanced RETROFIT with the PPPs improve lifetime by as much as 0.64× and 5.4× in the average case, respectively, over state-of-the-art row-level method while also reducing area overhead. In the worst-case scenario, these improvements further increase to 2.6× and 16.0×. Combined with the proposed column-level WL, enhanced RETROFIT realizes an overall 1.5× memory lifetime improvement over the perfectly uniform wear-leveling with equal storage overhead.

Error detection and correction which has been used in communication and memory design is becoming increasingly important in fault tolerant logic circuit design. As a result of the aggressive technology scaling, the current high-density integrated circuits are easily succumbed to faulty operations generated from many sources including stuck-at-faults, radiation induced faults, or malicious eavesdropper attacks. The currently used techniques like low-density parity-check (LDPC) and Hamming code based fault masking to mitigate bit flips in the digital circuits are either single bit error correcting or multiple error correctable with Bose-Choudhury-Hocquenghem (BCH) and Reed-solomon based methods with very large overheads. This paper introduce a novel cross code based method that can correct multiple errors with minimal compromise in error correction capability and area. The key idea of the novel method proposed in this paper is that do not correct all the errors but minimize their probability being escaped. Experimental results of the proposed methods show that the following: (1) area overhead is 101% for Hamming cross code and 106% for BCH cross code for a 90-bit finite field multiplier and (2) 150% for Hamming cross code and 170% for BCH cross codes for practically used 163-bit digit serial polynomial basis multiplier. Thus, the proposed methods are significantly efficient compared to Triple Modular Redundancy (TMR), LDPC, Hamming based methods in terms of area overhead and also the first attempted approach to a low complexity multiple error correctable digit serial multiplier to the best of the authors knowledge.

Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes

Computational approaches to the analysis of collective behavior in social insects increasingly rely on motion paths as an intermediate data layer from which one can infer individual behaviors or social interactions. Honey bees are a popular model for learning and memory. Previous experience has been shown to affect and modulate future social interactions. So far, no lifetime history observations have been reported for all bees of a colony. In a previous work we introduced a recording setup customized to track up to 4,000 marked bees over several weeks. Due to detection and decoding errors of the bee markers, linking the correct correspondences through time is non-trivial. In this contribution we present an in-depth description of the underlying multi-step algorithm which produces motion paths, and also improves the marker decoding accuracy significantly. The proposed solution employs two classifiers to predict the correspondence of two consecutive detections in the first step, and two tracklets in the second. We automatically tracked ~2,000 marked honey bees over 10 weeks with inexpensive recording hardware using markers without any error correction bits. We found that the proposed two-step tracking reduced incorrect ID decodings from initially ~13% to around 2% post-tracking. Alongside this paper, we publish the first trajectory dataset for all bees in a colony, extracted from ~3 million images covering 3 days. We invite researchers to join the collective scientific effort to investigate this intriguing animal system. All components of our system are open-source.

When transmitting a sampled signal digitally, data and error correction bits must be transmitted at least as fast as the sampling rate. Typically, each bit is allocated the same transmission time interval, which means the optimal detector yields the same error probability for each bit. An alternative is to vary the bit interval duration according to the bit's contribution to the reconstructed sample. The optimal solution yields significant gains in mean-squared error (several dB) over that provided by equal-duration bit intervals. These gains occurred over a wide range of signal-to-noise ratios. When block error correction is performed, we derive the optimal decoder from a Bayesian viewpoint and show that gains obtain here as well.

This paper investigates the effects of noise‐induced transmission errors on the performance of compression coding methods for still pictures. The following four coding methods are considered: (1) adaptive cosine transform coding; (2) DPCM coding; (3) adaptive block coding; and (4) vector quantization coding. First, the relations among the bit error rate, signal‐to‐noise ratio (SNR), and code lengths by these coding methods are compared in the case of transmission without error control. Adaptive cosine transform coding and adaptive block coding require control information for adaptivity; therefore, they are investigated with and without transmission errors in the coding control information. Further, transmission with error control is studied for sending control information. Considering the error control methods, both automatic repeat request and forward error correction are considered. In these cases SNR deterioration by transmission noise beyond error correction capability and the amount of additional data required for error detection/correction or retransmission are examined. BCH codes are used for error detection and correction.

ARQ methods of error control can considerably improve the reliablity of data transmission in such areas as satellite communications, computer networks, etc. A number of ARQ schemes using both block and convolutional codes have appeared in the literature. In this paper, the following problem is addressed. Given two different implementations of an ARQ scheme, one using a block code and the other using a convolutional code, such that the bit error probability of both implementations does not exceed some specific value, which implementation has the higher throughput and under what conditions will it be attained? The comparison is made for three basic retransmission schemes using both hybrid and pure ARQ: stop-and-wait, go-back- N , and selective repeat. Numerical estimates of the throughput were obtained using approximate theoretical expressions for BCH codes and simulation results for sequential decoding of rate 1/2 convolutional codes. Parameters optimizing the performance of both block and convolutional codes for different channel conditions and round trip delays were found and were used to obtain these numerical estimates. Comparison of the quantitative results indicates a trend toward preferring convolutional codes as delay and/or block length increases. A binary symmetric channel with noiseless feedback was assumed. Possible implications for the Gaussian channel are also discussed.

The various codes are used for the error detection and correction in the field of communication. Some are for the single bit error and some are for the multiple bits error. Reed-Muller algorithm realizes the ability of multiple bits error detection and correction. With the superior error correction capability, these codes have initiated wide scale interests in satellite communication, wireless communication, and storage fields. Reed-Muller codes cover a wide range of service requirements and diverse interference conditions in wireless applications and can operate at both high and low code rates. In this paper, the comparison of Reed-Muller codes with different other codes for error detection and correction of multiple bits is proposed and further we can implement it on a Xilinx field programmable gate array (FPGA) device. Using Reed-Muller method the data is transferred from transmitter to receiver without any error. The error detection and correction principle and realization methods are described in detail. The multiple bits error detection and correction with Reed-Muller algorithm method can improve the bit error rate and packet error rate effectively.

A code is presented which is designed to protect a 64 bit word, consisting of 8 bytes of 8 bits each, against both byte errors and single bit errors occurring in computer memories. Two check bytes are appended to give an overall length of 80 bits. The code then provides the often studied SEC-BED-DED level of error protection; that is, single error correction, byte error detection and double error detection are available simultaneously. In addition, the code detects a byte error together with a single random error occurring concurrently in another byte. Some implementation issues such as systematic versus separable encoding are considered. >

In nanoscale technologies, memories are vulnerable to both parametric failures, as well as, runtime failures induced by “soft errors” such as voltage, or thermal noise and aging effects. This chapter addresses the runtime failures in on-chip memories induced by “soft errors”. Conventionally such runtime errors are addressed using single error correction double error detection (SECDED) codes. However, these codes have very limited correction capability, making them inefficient to protect memory in scaled technologies (sub-45 nm), which are particularly vulnerable to multiple-bit failures (Hareland et al. Characterization of Multi-bit Soft Error events in advanced SRAMs, Intl. Electron Devices Meeting, 2003; Osada et al. IEEE J Solid State Circ 39(5), 2004). The requirement to tolerate multi-bit failures is accentuated by inter-die and intra-die variation in memory blocks which increases the vulnerability towards runtime failures. This chapter explores architectural modifications and a novel reconfigurable error-control coding (ECC) technique which together can be extremely effective in protecting on-chip memories against runtime failures.

The authors propose a novel design method for single b-bit byte error correcting and double bit error detecting code, called Sb EC-DED code, suitable for high-speed memory systems using byte organized RAM chips. This type of byte error control code is practical from the viewpoint of having less redundancy and stronger error control capability than the existing codes. A code design method using elements from a coset of a subfield under addition gives the practical Sb EC-DED code with 64 information bits and 4-bit byte length which has the same check-bit length, 12 bits, as that of the single byte error correcting code. This also has very high error detection capabilities of random double byte errors and of random triple bit errors. >