LTE physical layer implementation based on GPP multi-core parallel processing and USRP platform

Efficient and effective broadband wireless technologies are required to support the foreseeable need to process and exchange large amounts of data. In this Special Issue of the Springer Journal of Signal Processing Systems various disciplines of such efficiency and effectiveness in the context of Software-Defined Radio (SDR) technologies are discussed. At first, a selection of articles focuses on “spectral efficiency”. Since frequency spectrum is known to be scarce and limited, it becomes a resource of increasing value whose utilization must be handled with care. The rapidly growing demand for higher data throughputs in wireless communication does not allow inefficient use of spectrum anymore. Two promising approaches to tackle the “spectral efficiency” issue are Cognitive Radio (CR) and Dynamic Spectrum Access (DSA). A Cognitive Radio is capable of learning and adapting to its transmission environment. Taking e.g. spectrum sensing results into account, the decisions for accessing the scarce frequency spectrum in the most flexible and effective manner are made. CRs are typically based on SDR technology. Thus, the first set of articles puts emphasis on topics in the areas of Cognitive Radio, Cognitive Radio Networks, and Spectrum Sensing. The second selection of articles addresses the problems of “energy efficiency” and “implementation efficiency”. Especially in wireless communications these types of efficiencies are highly important to increase battery time of modern SDRbased platforms. The architectures of such SDRs are typically based on heterogeneous multi-processor hardware platforms hosting General Purpose Processors (GPP), Digital Signal Processors (DSP), Field Programmable Gate Arrays (FPGA) and sometimes even more specific processing elements. Each type of processor has a specific advantage in one or the other performance criterion like energy consumption, flexibility, processing time, throughput, waveform portability, components reusability etc. Whenever a new waveform shall be implemented on an SDR, the system designer has to take the decision for the best possible trade-off between all of these, partly conflicting, criteria under the given circumstances. For instance, the portability of waveform components can be improved by fulfilling the constraints of the Software Communications Architecture (SCA) specification and by using common Application Programming Interfaces (API). Thus, the second set of articles puts particular emphasis on topics in the areas of SDR and SCA Implementations.

Software defined radios (SDR) can be found in every area of wireless signal processing. SDRs realized so far are mostly part of communication technology, including audio broadcast receivers. Image- and video processing in SDRs is not common due to the fact that this type of real-time application requires a huge amount of processing resources. It can be foreseen that SDRs for video processing will be the next attractive approach for flexible and cost-effective media systems. We started with functional diagrams of the required modules for TV receivers, selected suitable algorithms to estimate their computational complexity and investigated their resource-quality scaling properties. Thereafter benchmark tests were done for a variety of common general purpose processors (GPPs), showing that real-time performance will be possible in the near future.

New wireless communications standards do not replace old ones, instead the number of standards keeps on increasing and by now an abundance of standards exists. Moreover there is no reason to assume that this trend will ever stop. Therefore, the software-radio concept is emerging as a potential pragmatic solution: a software implementation of the user terminal able to dynamically adapt to the radio environment in which the terminal is located. For manufacturers this could result in shorter development time, cheaper production due to higher volumes. Furthermore software radio has advantages for consumers because it enables only software updates for new functionality without new hardware. Because of the analog nature of the air interface, a software radio will always have an analog front-end. In an ideal software radio, the analog-to-digital converter (ADC) and the digital-to-analog converter (DAC) are positioned directly after the antenna. Such an implementation is not feasible due to the power that such a device would consume and other physical limitations. It is therefore a challenge to design a system that preserves most properties of the ideal software radio while being realizable with current-day technology. Such a system is called a software-defined radio (SDR). A flexible, all-standard radio will consume more energy than a dedicated radio for a single standard. The first flexible radio could be an application where power consumption is less an issue; an example being a flexible radio in a notebook. This thesis presents such a radio with the focus on wireless LAN standards. These standards use phase modulation or OFDM in the $2.4$ GHz or $5$ GHz frequency band, so we decided in our project to combine a receiver of a phase modulation standard (Bluetooth) with an OFDM receiver (HiperLAN/2) first. In our view SDR is an implementation technology: the HiperLAN/2 hardware is that complex to the Bluetooth hardware that the Bluetooth receiver may be added to the HiperLAN/2 one at limited costs. In this thesis we describe how the physical layer of the OSI model of a phase-modulation receiver can be combined with an OFDM receiver at a functional level. The second goal of this research is to investigate whether this combined receiver can be implemented in software running on a General Purpose Processor (GPP) and estimate the costs of such an implementation with respect to power consumption and computational power requirements. For this reason, a testbed has been developed where all baseband physical layer functions have been successfully mapped on a Pentium 4 processor. This has been tested in combination with a CMOS-integrated wideband analog SDR front-end, containing a low noise amplifier, down-conversion mixers and filters. The testbed can be extended to other standards, because the only limitations in our testbed are the maximal channel bandwidth of $20$ MHz, the dynamic range of the wideband SDR analog front-end and the processing capabilities of the used PC. In 1999, Bose showed for second-generation mobile standards that it is possible to perform most baseband functions of the physical layer on a GPP processor. In his research, I/O was one of the main bottlenecks. In thesis we have identified that this is no longer true for current-day computers. Nowadays, an important bottleneck is the latency of the operating system, because wireless standards require fast response times. Major contributions of this thesis to the field of SDR research are extending the work of Bose for wireless LAN standards and developing a functional SDR receiver architecture that is capable of receiving standards that use OFDM or phase modulation.

This paper presents Sora, a fully programmable software radio platform on commodity PC architectures. Sora combines the performance and fidelity of hardware software-defined radio (SDR) platforms with the programmability and flexibility of general-purpose processor (GPP) SDR platforms. Sora uses both hardware and software techniques to address the challenges of using PC architectures for high-speed SDR. The Sora hardware components consist of a radio front-end for reception and transmission, and a radio control board for high-throughput, low-latency data transfer between radio and host memories. Sora makes extensive use of features of contemporary processor architectures to accelerate wireless protocol processing and satisfy protocol timing requirements, including using dedicated CPU cores, large low-latency caches to store lookup tables, and SIMD processor extensions for highly efficient physical layer processing on GPPs. Using the Sora platform, we have developed a few demonstration wireless systems, including SoftWiFi, an 802.11a/b/g implementation that seamlessly interoperates with commercial 802.11 NICs at all modulation rates, and SoftLTE, a 3GPP LTE uplink PHY implementation that supports up to 43.8Mbps data rate.

We propose a low complexity synchronization method for the 3rd Generation Partnership Project (3GPP) long term evolution (LTE) mobile communication systems. A low complexity detection window, synchronization state machine, and two-stage detection are used to lower the computational complexity. The positions of the detection window and received samples are recorded, and the position and length of the detection window are controlled by the state machine. The positions are compared to decide if the received sample is useful for synchronization signal detection. Such techniques avoid unnecessary computations especially when implementing a receiver on a software defined radio (SDR) platform with general-purpose processors. We analyze the computational complexity of the proposed method and evaluate its performance based on simulations and using a Universal Software Radio Peripheral (USRP)-based SDR platform. The evaluation shows that the proposed method provides reliable and real-time synchronization signals on the considered SDR platform.

Feedback controllers were originally implemented using special-purpose hardware - whether as special-purpose circuits in electronic amplifiers and radio receivers, or as electronic/pneumatic/mechanical devices for process control. Over the last 30 years or so they have increasingly been implemented as software algorithms in general-purpose processors or microcontrollers. Today the increasing availability and programmability of specialpurpose electronic hardware, in particular field-programmable gate arrays (FPGA) and graphical processing units (GPU), offer the possibility of a return to special-purpose hardware for the implementation of controllers. Model predictive control (MPC) in particular has been a very successful class of algorithms for process control, and there is much current interest in applying it more widely, in particular to high-bandwidth systems which require very short control update intervals. However, MPC relies on solving numerical optimisation problems online and in real time, so the computation time is often the main bottleneck preventing the adoption of MPC. Most of the papers in this Special Issue are devoted to speeding up MPC computations, mostly by using special-purpose hardware.

In this demo, we will show the wireless Internet of Things (IoT) platform based on software defined radio (SDR) technology, and demonstrate its interference mitigation capability through cognitive radio technology. Video surveillance and temperature sensing are integrated on this platform as typical applications. This wireless platform is composed of the wireless edge appliance (WEA) as the base station and the wireless access appliance (WAA) as customer premises equipment (CPE). The WEA is based on a general IT device with general purpose processor (GPP), such as a laptop. Through unique optimization techniques, the base band signal processing can be completed on it with high speed. The WAA is an embedded system for low power and low cost. The Ethernet based interface between RRU and BBU is the first design with industry level in the world. Because it's high flexibility, stability and reliability, the platform can be used as the basic communication infrastructure in IoT applications, such as smart grid, pipeline monitoring, etc.

This article presents a deployment strategy to optimally manage the computing resource in the Software Defined Radio (SDR) equipment. The proposed solution is a combination of Reinforcement Learning and the run-time resource data of the communication system. Two scenarios, based on the traditional method and Reinforcement Learning, are made through the SDR virtual platform. The simulation results show that the proposed method expands the new module for General Purpose Processor (GPP) resources management and improves the performance of Cognitive Radio (CR). The method innovatively optimizes component deployment in multi-processor platforms and adapts to the CR equipment with the new generation heterogeneous chips so that to implement more applications when resources are limited.

Domain specific languages (DSLs) offer the potential for using a small, specialized and highly expressive programming language to concisely represent solutions for a particular domain of problems. The DSL approach is in stark contrast to that of a general programming language that attempts to provide a means to represent solutions for a broad range of problems. DSLs may incorporate constructs and syntactical features that not only relate to the problem context, but also to the execution platform. DSLs thus provide a potential for reducing development time and thereby cutting business costs. At present this approach is likely more appropriate to prototyping and rapid experimental work; but as technologies to implement DSLs improve they may become more beneficial and cost effective for developing marketable products. In this paper we present a DSL, called OptiSDR, aimed to improve developer productivity for development of software defined radio (SDR) applications deployed on heterogeneous computing architectures (HCAs). OptiSDR is designed for HCAs that adhere to certain combinations of processing devices, namely FPGAs, graphics processing units, and multi-core general purpose processors. Our aim to improve developer productivity in multiple ways was achieved, with development cycles for parallel DSP routines for SDR reduced to few hours as opposed to days for CUDA-C development cycles. OptiSDR uses automatic code generation for structured parallel SDR patterns, and performs automatic profiling to generate faster execution kernels with speed-ups of more than 50× compared to other sequential implementations while reducing manual effort in porting and tuning code. Therefore this paper reports on a study confirming the potential to speed up when using OptiSDR for prototyping SDR applications.

Software defined radio (SDR) transitions the communication signal processing chain from a rigid hardware platform to a user-controlled paradigm, allowing unprecedented levels of flexibility in parameter settings. However, programming and operating such SDRs have typically required deep knowledge of the operating environment and intricate tuning of existing code, which adds delay and overhead to the network design. In this work, we describe a bi-directional transceiver implemented in MATLAB that runs on the USRP platform and allows automated, optimal selection of the parameters of the various processing blocks associated with a DBPSK physical layer. Further, we provide detailed information on how to create a real-time multi-threaded design wherein the same SDR switches between transmitter and receiver functions, using standard tools like the MATLAB Coder and MEX to speed up the processing steps. Our results reveal that link latency and packet reception accuracy are greatly improved through our approach, making it a viable first step towards protocol design within an easily accessible MATLAB environment.

We have proposed and evaluated a scalable architecture for implementing multi-gigabit protocol engines. The architecture utilizes a combination of custom-made VLSI circuitry and a general-purpose processor, such as the Intel 960 or the IBM PowerPC 403. Time critical operations such as line coding/decoding, CRC generation/checking, context-independent header processing, and buffer management are implemented in the customized VLSI part. These designs are never-the-less scalable and can be cascaded to further increase throughput. Some of the packet level processing, such as context-dependent header processing, are performed by the general-purpose processor. As processing power increases, more and more functions can be included in the general purpose processor. The throughput of this architecture is shown to be adequate for the operations and bit rates currently specified by Fibre Channel. Future CMOS technology advances will have the potential to further improve the raw throughput.

Wireless baseband processing, which is characterized by high computational complexity and high data throughput, is regarded as the most challenging issue for software radio (SR) systems, especially for the General Purpose Processor (GPP)-based SR systems. To overcome this implementation difficulty in SR systems, the multicore architecture has been proposed as the GPP-based SR platform, for example, multicore Central Processing Unit (CPU), Graphic Processing Unit (GPU) and Cell processors. In this paper, the Cell processor is considered as the core component in the GPP-based SR platform, and the channel decoding modules for convolutional, Turbo and Low-density parity-check (LDPC) codes of WiMAX systems are investigated and efficiently implemented on Cell processor. With a single Synergistic Processor Element (SPE) running at 3.2GHz, the implemented channel decoders can throughput up to 30Mbps, 1.36Mbps and 1.71Mbps for the above three codes, respectively. Moreover, the decoding modules can be easily integrated to the SR system and can provide a highly integrated SR solution.

Mobile devices execute applications with diverse compute and performance demands. This paper proposes a general purpose processor that adapts the underlying hardware to a given workload. Existing mobile processors need to utilize more complex heterogeneous substrates to deliver the demanded performance. They incorporate different cores and specialized accelerators. On the contrary, our processor utilizes only modest homogeneous cores and dynamically provides an execution substrate suitable to accelerate a particular workload. Instead of incorporating accelerators, the processor reconfigures one or more cores into accelerators on-the-fly. It improves performance with minimal hardware additions. The accelerators are made of general purpose ALUs reconfigured into a compute fabric and the general purpose pipeline that streams data through the fabric. To enable reconfiguration of ALUs into the fabric, the floorplan of a 4-core processor is changed to place the ALUs in close proximity on the chip. A configurable switched network is added to couple and dynamically reconfigure the ALUs to perform computation of frequently repeated regions, instead of executing general purpose instructions. Through this reconfiguration, the mobile processor specializes its substrate for a given workload and maximizes performance of the existing resources. Our results show that reconfiguration accelerates a set of selected compute intensive workloads by 1.56×, 2,39×, 3,51×, when configuring the accelerator of 1-, 2-, or 4- cores respectively.

This work contributes to the virtualization of the physical layer of wireless communication protocols, with focus on LTE. It describes the implementation of the uplink receiver side symbol processing functions of LTE at the base station physical layer, using a general-purpose computer equipped with a GPU. We describe the system components and the functions parallelization needed to make the virtualization process compatible with real-time operation, showing the bottlenecks of a software solution to make the LTE physical layer run on general purpose computers. Our validation experiments with a worst-case LTE frame scenario show the feasibility of the CPU/GPU approach. Moreover, since LTE uses common techniques with other wireless protocols, the presented results can also guide other virtualization efforts.

Due to the rapid growth of Internet, there is an increasing need for efficiently classifying packets with many header fields in large rule sets. For example, in Software Defined Networking (SDN), the OpenFlow table lookup can require 15 packet header fields to be examined. In this paper, we present several decomposition-based packet classification implementations with efficient optimization techniques. In the searching phase, packet headers are split or combined. In the merging phase, the partial searching results from all the fields are merged to generate the final result. We prototype our implementations on state-of-the-art Field Programmable Gate Array (FPGA), multi-core General Purpose Processor (GPP), and Graphics Processing Unit (GPU). On FPGA, we propose two optimization techniques to divide generic ranges; modular processing elements are constructed and concatenated into a systolic array. On multi-core GPP, we parallelize both the searching and merging phases using parallel program threads. On the GPU-accelerated platform, we minimize branch divergence and reduce the data communication overhead. Experimental results show that 500 Million Packets Per Second (MPPS) throughput and 3 us latency can be achieved for 1.5 K rule sets on FPGA. We achieve 14.7 MPPS throughput and 30.5 MPPS throughput for 32 K rule sets on multi-core GPP and GPU-accelerated platforms, respectively. As a heterogeneous solution, our GPU-accelerated packet classifier shows 2X speedup compared to the implementation using multi-core GPP only. Compared with prior works, our designs can match long packet headers against very complex rule sets.