LV-MAGIC: Logic Synthesis and Verification for MAGIC based In-Memory Computing

Jiaxiang Pan; Yinshui Xia; Lunyao Wang; Zhufei Chu

doi:10.1109/tcad.2026.3652093

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LV-MAGIC: Logic Synthesis and Verification for MAGIC based In-Memory Computing

https://doi.org/10.1109/tcad.2026.3652093

LV-MAGIC: Logic Synthesis and Verification for MAGIC based In-Memory Computing

Jan 1, 2026
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Jiaxiang Pan +3 more

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Abstract

In-memory computing shows great potential for data-intensive applications, with memristor-aided logic (MAGIC) being a key enabler. Efficient electronic design automation (EDA) tools are essential for implementing arbitrary Boolean functions in this paradigm. This paper presents a logic synthesis and verification framework for MAGIC-based in-memory computing, enabling the mapping of Boolean functions to memristor arrays, generation of micro-operations, and verification of results. To improve upon previous approaches, we introduce an area-aware mapping tool that optimizes the utilization of resistive random-access memory (RRAM). During logic synthesis, we propose a reinforcement learning (RL)-based tool for automatically generating optimized sequence flows, adapting to network characteristics for better mapping. To verify the mapping correctness, we introduce an equivalence verification tool that uses circuit structure for fast validation, also identifying bugs missed by previous methods. Experimental results show that our mapping tool reduces RRAM usage by 13% and 10% on average, with minimal increases of 1% and 2% in computation cycles, compared to state-of-the-art techniques. Additionally, the proposed synthesis recipe generation tool outperforms fixed flows and three heuristic algorithms (greedy, simulated annealing, and genetic algorithms), reducing the area-delay product by 21% and 6% for the ISCAS’85 and EPFL benchmarks, respectively.

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