Machine learning for run-time energy optimisation in many-core systems

Nowadays clusters are one of the most used platforms in High Performance Computing and most programmers use the Message Passing Interface (MPI) library to program their applications in these distributed platforms getting their maximum performance, although it is a complex task. On the other side, OpenMP has been established as the de facto standard to program applications on shared memory platforms because it is easy to use and obtains good performance without too much effort. So, could it be possible to join both worlds? Could programmers use the easiness of OpenMP in distributed platforms? A lot of researchers think so. And one of the developed ideas is the distributed shared memory (DSM), a software layer on top of a distributed platform giving an abstract shared memory view to the applications. Even though it seems a good solution it also has some inconveniences. The memory coherence between the nodes in the platform is difficult to maintain (complex management, scalability issues, high overhead and others) and the latency of the remote-memory accesses which can be orders of magnitude greater than on a shared bus due to the interconnection network. Therefore this research improves the performance of OpenMP applications being executed on distributed memory platforms using a DSM with sequential consistency evaluating thoroughly the results from the NAS parallel benchmarks. The vast majority of designed DSMs use a relaxed consistency model because it avoids some major problems in the area. In contrast, we use a sequential consistency model because we think that showing these potential problems that otherwise are hidden may allow the finding of some solutions and, therefore, apply them to both models. The main idea behind this work is that both runtimes, the OpenMP and the DSM layer, should cooperate to achieve good performance, otherwise they interfere one each other trashing the final performance of applications. We develop three different contributions to improve the performance of these applications: (a) a technique to avoid false sharing at runtime, (b) a technique to mimic the MPI behaviour, where produced data is forwarded to their consumers and, finally, (c) a mechanism to avoid the network congestion due to the DSM coherence messages. The NAS Parallel Benchmarks are used to test the contributions. The results of this work shows that the false-sharing problem is a relative problem depending on each application. Another result is the importance to move the data flow outside of the critical path and to use techniques that forwards data as early as possible, similar to MPI, benefits the final application performance. Additionally, this data movement is usually concentrated at single points and affects the application performance due to the limited bandwidth of the network. Therefore it is necessary to provide mechanisms that allows the distribution of this data through the computation time using an otherwise idle network. Finally, results shows that the proposed contributions improve the performance of OpenMP applications on this kind of environments.

[ACCESS RESTRICTED TO THE UNIVERSITY OF MISSOURI AT REQUEST OF AUTHOR.] In recent years, most scientific research in both academia and industry has become increasingly data-driven. According to market estimates, spending related to supporting scientific data-intensive research is expected to increase to $5.8 billion by 2018. Particularly for data-intensive scientific fields such as bioscience, or particle physics within academic environments, data storage/processing facilities, expert collaborators and specialized computing resources do not always reside within campus boundaries. With the growing trend of large collaborative partnerships involving researchers, expensive scientific instruments and high performance computing centers, experiments and simulations produce peta-bytes of data viz., Big Data, that is likely to be shared and analyzed by scientists in multi-disciplinary areas. Federated multi-cloud resource allocation for data-intensive application workflows is generally performed based on performance or quality of service (i.e., QSpecs) considerations. At the same time, end-to-end security requirements of these workflows across multiple domains are considered as an afterthought due to lack of standardized formalization methods. Consequently, diverse/heterogenous domain resource and security policies cause inter-conflicts between application's security and performance requirements that lead to sub-optimal resource allocations, especially when multiple such applications contend for limited resources. In this thesis, a joint performance and security-driven federated resource allocation scheme for data-intensive scientific applications is presented. In order to aid joint resource brokering among multi-cloud domains with diverse/heterogenous security postures, the definition and characterization of a data-intensive application's security specifications (i.e., SSpecs) is required. Next, an alignment technique inspired by Portunes Algebra to homogenize the various domain resource policies (i.e., RSpecs) along an application's workflow lifecycle stages is presented. Using such formalization and alignment, a near optimal cost-aware joint QSpecs-SSpecs-driven, RSpecs-compliant resource allocation algorithm for multi-cloud computing resource domain/location selection as well as network path selection, is proposed. We implement our security formalization, alignment, and allocation scheme as a framework, viz., "OnTimeURB" and validate it in a multi-cloud environment with exemplar data-intensive application workflows involving distributed computing and remote instrumentation use cases with different performance and security requirements.

Many applications vary a lot in execution time depending on their workload. A prominent example is image processing applications, where the execution time is dependent on the content or the size of the processed input images. An interesting case is when these applications have quality-of-service requirements such as soft deadlines, that they should meet as good as possible. A further complicated case is when such applications have one or even multiple further objectives to optimize like, e.g., energy consumption. Approaches that dynamically adapt the processing resources to application needs under multiple optimization goals and constraints can be characterized into the application-specific and feedback-based techniques. Whereas application-specific approaches typically statically use an offline stage to determine the best configuration for each known workload, feedback-based approaches, using, e.g., control theory, adapt the system without the need of knowing the effect of workload on these goals. In this paper, we evaluate a state-of-the-art approach of each of the two categories and compare them for image processing applications in terms of energy consumption and number of deadline misses on a given many-core architecture. In addition, we propose a second feedback-based approach that is based on finite state machines (FSMs). The obtained results suggest that whereas the state-of-the-art application-specific approach is able to meet a specified latency deadline whenever possible while consuming the least amount of energy, it requires a perfect characterization of the workload on a given many-core system. If such knowledge is not available, the feedback-based approaches have their strengths in achieving comparable energy savings, but missing deadlines more often.

Aggressive technology scaling enabled very high integration density. Unfortunately, it also led to issues such as process variation, increased power density and consequently rising chip temperature resulting in accelerated device aging and poor lifetime reliability of different components in a manycore system. Moreover, thermal and power limitations let only a fraction of the chip function at full speed; the rest is the dark silicon. Most of the lifetime reliability enhancement solutions for the multi-/manycore systems in the literature are heuristic-based, while some use standard compute-intensive methods to solve the optimization problem making them not scale well with the manycore size. The heuristic-based solutions are formulated to search through the design space of a fine granularity making it huge, limiting their scalability. Also, these approaches do not account for the impact of different applications' execution behavior on the aging of the underlying cores, and their performance requirement distribution across the cores to their advantage. In this paper, we present our resource management strategies towards building scalable lifetime reliability enhancement solutions for dark silicon manycore systems. The first technique, Hierarchical Mapping approach (HiMap), maps a periodic workload employing a block-based hierarchical method that leverages dark cores for thermal mitigation. The second approach, LifeGuard, uses reinforcement learning to learn the applications' aging behavior, and is aware of the performance requirement pattern onto the core frequencies. It maps randomly arriving requests and is scalable to the number of applications and the size of a manycore.

A multi-layered performance analysis for cloud-based topic detection and tracking in Big Data applications

Heterogeneous multi-core platforms that contain different types of cores, organized as clusters, are emerging, e.g., ARM’s big.LITTLE architecture. These platforms often need to deal with multiple applications, having different performance requirements, executing concurrently. This leads to the generation of varying and mixed workloads (e.g., compute and memory intensive) due to resource sharing. Run-time management is required for adapting to such performance requirements and workload variabilities and to achieve energy efficiency. Moreover, the management becomes challenging when the applications are multi-threaded and the heterogeneity needs to be exploited. The existing run-time management approaches do not efficiently exploit cores situated in different clusters simultaneously (referred to as inter-cluster exploitation) and DVFS potential of cores, which is the aim of this paper. Such exploitation might help to satisfy the performance requirement while achieving energy savings at the same time. Therefore, in this paper, we propose a run-time management approach that first selects thread-to-core mapping based on the performance requirements and resource availability. Then, it applies online adaptation by adjusting the voltage-frequency ( V-f ) levels to achieve energy optimization, without trading-off application performance. For thread-to-core mapping, offline profiled results are used, which contain performance and energy characteristics of applications when executed on the heterogeneous platform by using different types of cores in various possible combinations. For an application, thread-to-core mapping process defines the number of used cores and their type, which are situated in different clusters. The online adaptation process classifies the inherent workload characteristics of concurrently executing applications, incurring a lower overhead than existing learning-based approaches as demonstrated in this paper. The classification of workload is performed using the metric Memory Reads Per Instruction (MRPI). The adaptation process pro-actively selects an appropriate V-f pair for a predicted workload. Subsequently, it monitors the workload prediction error and performance loss, quantified by instructions per second (IPS), and adjusts the chosen V-f to compensate. We validate the proposed run-time management approach on a hardware platform, the Odroid-XU3, with various combinations of multi-threaded applications from PARSEC and SPLASH benchmarks. Results show an average improvement in energy efficiency up to 33 percent compared to existing approaches while meeting the performance requirements.

In many deployments, computer systems are underutilized -- meaning that applications have performance requirements that demand less than full system capacity. Ideally, we would take advantage of this under-utilization by allocating system resources so that the performance requirements are met and energy is minimized. This optimization problem is complicated by the fact that the performance and power consumption of various system configurations are often application -- or even input -- dependent. Thus, practically, minimizing energy for a performance constraint requires fast, accurate estimations of application-dependent performance and power tradeoffs. This paper investigates machine learning techniques that enable energy savings by learning Pareto-optimal power and performance tradeoffs. Specifically, we propose LEO, a probabilistic graphical model-based learning system that provides accurate online estimates of an application's power and performance as a function of system configuration. We compare LEO to (1) offline learning, (2) online learning, (3) a heuristic approach, and (4) the true optimal solution. We find that LEO produces the most accurate estimates and near optimal energy savings.

Modeling the performance of non-deterministic parallel applications on future many-core systems requires the development of novel simulation and emulation techniques and tools. We present Prometheus, a fast, accurate and modular emulation framework for task-based applications. By raising the level of abstraction and focusing on runtime synchronization, Prometheus can accurately predict applications’ performance on very large many-core systems. We validate our emulation framework against two real platforms (AMD Interlagos and Intel MIC) and report error rates generally below 4%.We, then, evaluate Prometheus' performance and scalability: our results show that Prometheus can emulate a task-based application on a system with 512K cores in 11.5 hours. We present two test cases that show how Prometheus can be used to study the performance and behavior of systems that present some of the characteristics expected from exascale supercomputer nodes, such as active power management and processors with a high number of cores but reduced cache per core.

This paper proposes a directed acyclic graph (DAG) scheduling algorithm for cluster-based many-core architecture. Most of DAG scheduling methods that consider multiple processors and communication delays use a heuristic approach because it is difficult to shorten a schedule length (i.e.,makespan). Unfortunately, existing heuristic algorithms do not consider tasks that require a large number of computational resources. Such tasks typically need to be offloaded to a large-scale computational resource such as a many-core system or graphics processing unit (GPU). Therefore, we propose a DAG scheduling algorithm that uses a cluster-based many-core architecture to offload such computation; here, we use Kalray MPPA-256 as the many-core architecture. Our algorithm divides many-core computational resources for such tasks. Comparing our results with existing algorithms, we succeeded in shortening makespan with many types of DAGs while also considering Amdahl's law. We also compared the deadline miss ratio and execution time of our algorithm to existing algorithms, and show that the proposed algorithm is superior to the existing algorithms for any evaluation metrics.

Many-core architectures are omnipresent in today's modern life. They can be found in mobile phones, tablet computers, game consoles, laptops, desktop and server systems. Although, many-core systems are common in powerful mainstream systems, their core count is still in the lower tens and has not increased much over the last years. Truly massively parallel systems with core counts in the higher tens or even hundreds have only been seen so far in custom-made architectures for High Performance Computing systems or innovative new architectures from startup companies. Nevertheless, the core count has already reached acritical mass that shows the difficulty of increasing performance and reducing power. This requires careful orchestration of the many cores with efficient synchronization constructs such that they reduce the idle time of waiting cores and use power efficient synchronization operations.

Power consumption is crucial in embedded systems, mainly because of the limited battery capacity and the problem of heat dissipation. The energy efficiency of System-on-Chips (SoCs) is optimized at both hardware and software level using simulation platforms. The challenge of these platforms lies in the tradeoff between accuracy and simulation speed for early architecture exploration and HW/SW validation. In the context of many-core systems in which heavy software stacks are executed, fast simulation platforms are required. In this paper, we present our power modeling approach of a complex many-core system to estimate the power consumption of software applications executed on it. We propose in particular a light and accurate power model for VLIW processors, as this kind of processor is commonly used in such systems. The power estimator we set up is part of a practical power characterization framework fully automated that includes low level simulations which are then used to back-annotate fast simulation models. Our case study is the STHORM accelerator, a clustered many-core architecture comprising dual-instruction issue processors, a complex memory hierarchy and DMA engines. Experimental results show that we can perform fast power estimations with an estimation error lower than 4% for the VLIW cores, which are the main source of power consumption, and less than 10% for the overall SoC platform, and for a simulation time overhead lower than 1%.

Energy minimization of parallel applications is an emerging challenge for current and future generations of many-core computing systems. In this paper, we propose a novel and scalable energy minimization approach that suitably applies DVFS in the sequential part and jointly considers DVFS and dynamic core allocations in the parallel part. Fundamental to this approach is an iterative learning based control algorithm that adapt the voltage/frequency scaling and core allocations dynamically based on workload predictions and is guided by the CPU performance counters at regular intervals. The adaptation is facilitated through performance annotations in the application codes, defined in a modified OpenMP runtime library. The proposed approach is validated on an Intel Xeon E5-2630 platform with up to 24 CPUs running NAS parallel benchmark applications. We show that our proposed approach can effectively adapt to different architecture and core allocations and minimize energy consumption by up to 17% compared to the existing approaches for a given performance requirement.

The next flagship supercomputer in Japan, replacement of K supercomputer, is being designed toward general operation in 2020. Compute nodes, based on a manycore architecture, connected by a 6-D mesh/torus network is considered. A three level hierarchical storage system is taken into account. A heterogeneous operating system, Linux and a light-weight kernel, is designed to build suitable environments for applications. It cannot be possible without codesign of applications that the system software is designed to make maximum utilization of compute and storage resources. After a brief introduction of the post K supercomputer architecture, the design issues of the system software will be presented. Two big-data applications, genome processing and meteorological and global environmental predictions will be sketched out as target applications in the system software design. Then, it will be presented how these applications' demands affect the system software.

General aviation (GA) aircrews are using a few data link-supported operational services today, and more are becoming available each year. These services are implemented through applications. One or more applications that use data link for exchanging information will be needed to provide each of the services. What communications, navigation and surveillance (CNS) related features does a developer need to incorporate into an application? This paper describes the principles and performance requirements that should be considered when creating aviation-related applications. The primary focus is to describe the CNS features (principles and performance) of applications that a small aircraft transportation system (SATS) aircraft could implement in 2010. It covers applications that use air-to-ground and air-to-air data links to exchange information. The concepts described are the principles and performance requirements that apply to an application regardless of the data link used for the exchange of information. Thus, the concepts are considered to be link independent. The operational services described are: air traffic control (ATC), surveillance, flight information services (FIS), aircraft operations center (AOC), electronic mail, Web browsing, and air-to-air chat.

Transactional Memory(TM) is being studied widely by researchers, which is viewed as a new parallel programming model for synchronizing concurrent accesses to shared data object in multi-core or many-core systems. Research result shows that TM has a good performance over Lock using micro-benchmarks. The performance of real applications based on TM is still not clear. In this paper, we describe how to build Simulation System of Earthquake Precursory Observatory Equipment (SSEPOE) using Dynamic Software Transactional Memory (DSTM) and compare the scalability of it to that of lock-based one. Experimental result shows that the performance of SSEPOE based on STM have no advantages than lock-based one and it has a little convenience than lock in programming SSEPOE, this is because SSEPOE is rather simple and the experimentation computer only has two cores. If the computer has more cores and the real application is more complex, the version based on STM will outperform the lock-based one. Another hand, because DSTM2 did not support long transactions, SSEPOE Server did not realize all synchronization of threads using transactions. We only used transactions in the execution process of command instead of locks. We also gave insights into development techniques to encounter in developing SSEPOE Server and discussed the shortcomings of DSTM APIs.