Macromodeling of Digital MOS VLSI Circuits

Chapter 24 - GPU-Based Parallel Computing for Fast Circuit Optimization

Variational quantum algorithms (VQAs) have dominated literature as tools for demonstrating quantum utility on near-term quantum hardware, with applications in optimisation, quantum simulation, and machine learning. While researchers have studied how easy VQAs are to train, the effect of quantum noise on the classical optimisation process is still not well understood. Contrary to expectations, we find that twirling, which is commonly used in standard error-mitigation strategies to symmetrise noise, actually degrades performance in the variational setting, whereas preserving biased or non-unital noise can help classical optimisers find better solutions. Analytically, we study a universal quantum regression model and demonstrate that relatively uniform Pauli channels suppress gradient magnitudes and reduce expressivity, making optimisation more difficult. Conversely, asymmetric noise such as amplitude damping or biased Pauli channels introduces directional bias that can be exploited during optimisation. Numerical experiments on a variational eigensolver for the transverse-field Ising model confirm that non-unital noise yields lower-energy states compared to twirled noise. Finally, we show that coherent errors are fully mitigated by re-parameterisation. These findings challenge conventional noise-mitigation strategies and suggest that preserving noise biases may enhance VQA performance.

Nowadays, current passive mixers represent the state of the art for signal down-conversion in wireless receivers. In such kind of structures, noise, distortions and losses are strictly correlated to the performance of the stage following the mixer. The most common solution adopted to sense the down-converted current is a transimpedance amplifier (TIA) in shunt with a capacitance to ground that assures a low input impedance when the loop gain of the amplifier decreases (Fig. 20.9.1a). A low input impedance is necessary to have a small voltage swing at the output of the mixer (typically few hundreds mV) to minimize the modulation of the switch resistance and with it the distortion produced during the downconversion. The input capacitance can also be used to filter the majority of the out-of-band interferers by transforming the TIA into a filter [1,2] (Fig. 20.9.1b). This reduces the dynamic range required by the TIA and its power consumption. This advantage comes at a cost of area, since the limited voltage swing tolerable at the input of the TIA demands a large capacitor to absorb the downconverted interferers. This trade-off is relaxed with the proposed solution (Fig. 20.9.2), where the input capacitance (C1) is partially boosted by a feedback network minimizing the swing required at the input of the TIA. This idea, originally proposed in [3] only to improve the 1dB compression point, is now used to maximize the spurious-free dynamic range of the TIA, exploiting an intrinsic in-band highpass shaping of noise and distortion. Furthermore, an adaptive transfer function, which improves its filtering action in presence of large out-of-band interferers, is realized.

International audience

We propose a new family of smart pixel receivers which use a current-mode front-end and a current-to-voltage converter. The sensitivity and the power consumption of a current mode circuit are independent of the bit rate and input capacitance. The bandwidth is also independent of input capacitance. Typically, the input capacitance is large compared to the minimum gate capacitance. The current-mode front-end offers a potential advantage in terms of sensitivity and power if its switching current and its static power is small by providing a 'buffer' between the high capacitance of detectors.

Improving Resource Utilization for Arthroplasty Care by Leveraging Machine Learning and Optimization: A Systematic Review

A mechanics based prediction model for tool wear and power consumption in drilling operations and its applications

This is the second issue of the annual series of Vietnam Journal of Mathematics, which is named IWR Special Issue on Scientific Computing and is led by the Interdisciplinary Center for Scientific Computing (IWR) of Heidelberg University. This issue is dedicated to Prof. Hans Georg Bock, Director and former Managing Director of IWR, on the occasion of his 70th birthday, which he celebrated on May 9, 2018. It includes 16 papers written by authors having close ties to Hans Georg Bock. Their contributions cover various areas of Mathematics and its applications, reflecting Hans Georg Bock’s influence in Mathematical Modeling, Simulation, and Optimization and practical applications of Mathematics, an emerging key methodology for science, economy, and technology in the third millenium.

Capacitance sensors are widely used to measure various physical quantities, including position, pressure, and concentration of certain chemicals [1-6]. Integrating capacitive sensors into a small wireless sensor system is challenging due to their large power consumption relative to the total system power/energy budget, which can be as low as a few nW [4]. Typical capacitance-to-digital converters (CDCs) use charge sharing or charge transfer between capacitors to convert the sampled capacitance to voltage, which is then measured with an ADC [1-6]. This approach requires complex analog circuits, such as amplifiers and ADCs, increasing design complexity and often increasing power consumption. Moreover, the initial capacitance to voltage conversion essentially limits the input capacitance range because of output voltage saturation. This paper presents a fully digital CDC that is based on the observation that when a ring oscillator (RO) is powered from a charged capacitance, the number of RO cycles required to discharge the capacitance to a fixed voltage is naturally linear with the capacitance value. This observation enables a simple, fully digital conversion scheme that is inherently linear. As a result, the proposed CDC performs conversion across a very wide capacitance range from 0.7pF to over 10nF with < 0.06% linearity error. The CDC senses 11.3pF input capacitance with 35.1 pJ conversion energy and 141fJ/c-s FoM.

ABSTRACTIn this paper, a new low-power transimpedance amplifier (TIA) based on a modified Regulated Cascode (RGC) circuit structure followed by a closed-loop post-amplifier is proposed for 10 Gb/s applications. The main objective of this work is to reduce the power consumption while, the frequency bandwidth of the proposed amplifier is increased considerably. The booster of a conventional RGC is modified by a cascoded transistor and its effect on the performance of the circuit is studied mathematically, which are verified by simulations. The bandwidth extension is occurred due to increasing the gain of the booster amplifier in the RGC stage, which isolates further the input capacitance and results in a reduced input resistance value hence, a higher input pole frequency is obtained in comparison with other conventional RGC structures. On the other hand, by using an active inductive peaking technique, the frequency of the output pole is also increased which results in a further extension of the frequency bandwidth for the proposed circuit. The proposed TIA is simulated using 90 nm CMOS technology parameters, which shows a 50.5 dBΩ transimpedance gain, 7.3 GHz frequency bandwidth and 1.22 µArms input referred noise value for only 1 mW of power consumption at 1.2 V supply voltage.

This paper presents a compact, low power, digitally assisted differential capacitive-sensing readout circuit. It utilizes digital design and switch-based synchronous demodulator to reduce area and power consumption while improving the robustness of the system by diminishing the effects of interfering signals. To broaden the sensing range of the system, the simple implementation of a closed-loop configuration is employed to dynamically adjust the gain. This circuit is designed, analyzed, and laid out in a standard 0.35 μm CMOS technology from Austria Microsystems. Post-layout simulation results reveal that the proposed circuit is capable of resolving a minimum of 1fF changes in input capacitance under test.

An improved timing model for CMOS combinational logic is presented. The model is based on an analytical solution for the CMOS inverter output response to an input ramp. This model yields a better understanding of the switching behavior of the CMOS inverter than the step-response model by considering the slope of the input waveform. Essentially, the propagation delay is shown to be the sum of the step-response delay and an input dependent delay that may account for as much as 50-100 percent of the total delay. The matching between the ramp input and the characteristic input waveforms is shown to be easily performed for excellent agreement in output response and propagation delay. Even though the short-circuit current is neglected, its influence is shown to be small and may be corrected. As an example, the timing model is used to optimize CMOS output buffers for minimum delay. If the intrinsic output load capacitance is included in the model, the optimum tapering factor is shown to be not e but a value in the range 3-5 depending on process parameters and design style. Also, due to the input dependence of the propagation delay, the last inverter stage in the buffer should have a larger tapering factor than the other stages for minimum delay.

The first main result of this paper is the development of a low power threshold logic gate based on a capacitive input, charge recycling differential sense amplifier latch. The gate is shown to have very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations. The second main result is the development of a novel, low depth, carry look ahead addition scheme. One such adder is also designed using the proposed gate.

This paper presents a novel ultra low power wide-range four-quadrant multiplier/two-quadrant divider circuit. The proposed circuit is implemented using Floating Gate MOS (FGMOS) devices operating in weak inversion. The wide range is achieved by means of a predistortion technique based on having different input capacitances in the FGMOS transistors. The circuit compares favourably to other ultra low power multiplier/divider circuits. The multiplier/divider can operate under a 0.9V supply voltage with a power consumption of 87nW in a 0.35μm AMS technology.

This letter presents a 3-stage pipelined successive-approximation-resister (SAR) analog-to-digital converter (ADC) using a seven transistor-dynamic residue amplifier (7T-DA) for kickback noise cancelation. Thanks to the pipeline structure, the input capacitance is only 16 fF, achieving an effective resolution bandwidth (ERBW) of 2 GHz. The gain sensitivity to the temperature of the dynamic amplifier is reduced by an on-chip low-dropout voltage regulator (LDO) and a pulse generator. Fabricated in the 28-nm CMOS process, the prototype ADC running at 800 MS/s achieves a peak SNDR of 42.7 dB and SFDR of 52.0 dB at Nyquist input. It also achieves SNDR of 38.9 dB and SFDR of 49.9 dB at a 2-GHz input. The total power consumption of ADC is 1.55 mW, which corresponds to the Waldon figure of merit of 17.4 fJ/conv step and Schreier FoM of 156.8 dB, respectively.