Managing shared memory spaces in an object-oriented real-time simulation

GPUs provide high-bandwidth/low-latency on-chip shared memory and L1 cache to efficiently service a large number of concurrent memory requests. Specifically, concurrent memory requests accessing contiguous memory space are coalesced into warp-wide accesses. To support such large accesses to L1 cache with low latency, the size of L1 cache line is no smaller than that of warp-wide accesses. However, such L1 cache architecture cannot always be efficiently utilized when applications generate many memory requests with irregular access patterns especially due to branch and memory divergences that make requests uncoalesced and small. Furthermore, unlike L1 cache, the shared memory of GPUs is not often used in many applications, which essentially depends on programmers. In this article, we propose Elastic-Cache, which can efficiently support both fine- and coarse-grained L1 cache line management for applications with both regular and irregular memory access patterns to improve the L1 cache efficiency. Specifically, it can store 32- or 64-byte words in non-contiguous memory space to a single 128-byte cache line. Furthermore, it neither requires an extra memory structure nor reduces the capacity of L1 cache for tag storage, since it stores auxiliary tags for fine-grained L1 cache line managements in the shared memory space that is not fully used in many applications. To improve the bandwidth utilization of L1 cache with Elastic-Cache for fine-grained accesses, we further propose Elastic-Plus to issue 32-byte memory requests in parallel, which can reduce the processing latency of memory instructions and improve the throughput of GPUs. Our experiment result shows that Elastic-Cache improves the geometric-mean performance of applications with irregular memory access patterns by 104% without degrading the performance of applications with regular memory access patterns. Elastic-Plus outperforms Elastic-Cache and improves the performance of applications with irregular memory access patterns by 131%.

The MULTIPLUS project aims at the development of a modular parallel architecture suitable for the study of several aspects of parallelism in both true shared memory and virtual shared memory environments. The MULTIPLUS architecture is able to support up to 1024 Processing Elements based on SPARC microprocessors. The MULPLIX Unix-like operating system offers a suitable parallel programming environment for the MULTIPLUS architecture by providing facilities for the creation of threads, the allocation of private and shared memory space and the efficient use of synchronization primitives. After presenting the main features of the MULTIPLUS architecture and of the MULPLIX operating system, the paper describes in detail the design and the implementation of the three MULTIPLUS architecture basic hardware modules: the Processing Element, the Multistage Interconnection Network and the I/O Processor. In addition, the definition of the MULPLIX parallel programming primitives is discussed and their use is illustrated through an example. Finally, future directions in the development of the MULTIPLUS research project are commented.

Real-Time Image Processing is the key work in robot vision. With the limitation of the hardware technique, many algorithm-oriented firmware systems were designed in the past. But their architectures were not flexible enough to achieve a multi- algorithm development system. Because of the rapid development of microelectronics technique, many high performance DSP chips and high density FPGA chips have come to life, and this makes it possible to construct a more flexible architecture in real-time image processing system. In this paper, a Double DSP General Image Processing System (DDGIPS) is concerned. We try to construct a two-DSP-based FPGA-computational system with two TMS320C6201s. The TMS320C6x devices are fixed-point processors based on the advanced VLIW CPU, which has eight functional units, including two multipliers and six arithmetic logic units. These features make C6x a good candidate for a general purpose system. In our system, the two TMS320C6210s each has a local memory space, and they also have a shared system memory space which enable them to intercommunicate and exchange data efficiently. At the same time, they can be directly interconnected in star- shaped architecture. All of these are under the control of FPGA group. As the core of the system, FPGA plays a very important role: it takes charge of DPS control, DSP communication, memory space access arbitration and the communication between the system and the host machine. And taking advantage of reconfiguring FPGA, all of the interconnection between the two DSP or between DSP and FPGA can be changed. In this way, users can easily rebuild the real-time image processing system according to the data stream and the task of the application and gain great flexibility.

We present a randomized algorithm for asynchronous task allocation, also known as the write-all or do-all problem. Our algorithm has work complexity O(n+k <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> log <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> k) with high probability, where n the number of tasks and k the number of processes that participate in the computation. Our solution uses O(n) shared memory space that supports atomic test-and-set operations and with high probability each participating process uses O(k) internal memory space. This is the first adaptive solution for the write-all problem that has work n plus some additive term which depends only on the number of participating processes k and not the size of the problem n.

In this paper, we present a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. Specifically, we propose an optimization algorithm that targets the reduction of extra off-chip memory accesses caused by inter-processor communication. This is achieved by increasing the application-wide reuse of data that resides in the scratch-pad memories of processors. Our experimental results obtained on four array-intensive image processing applications indicate that exploiting inter-processor data sharing can reduce the energy-delay product by as much as 33.8% (and 24.3% on average) on a four-processor embedded system. The results also show that the proposed strategy is robust in the sense that it gives consistently good results over a wide range of several architectural parameters.

Current trends in computing require dedicated chips to speed up computing performances. These dedicated chips or ASICs are designed for specific applications, however, the drawback in this approach is that IC (Integrated Circuits) functionality cannot be changed. In areas where H/W programmability and reconfigurability is required, FPGA is the solution to achieve this. System on Chip (SOC) FPGAs (Field Programmable Gate Arrays) include processor hard blocks connected to fabric through various interconnects. This architecture provides better performance and the ability to run Operating Systems (OS) like Linux <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> that has direct access to programmable FPGA logic. This paper explains how to split the functions of an application code between hard block processor and FPGA fabric logic. OPUS is an open-source audio codec widely used in voice-over-IP (VoiP) applications. The codec execution can be accelerated by moving some of its functions to FPGA logic. One such function of OPUS code is implemented in FPGA logic using High-Level Synthesis (HLS). Shared DDR memory space is used to transfer the data between the processor and FPGA. In this paper, we summarize the reduction in execution time and processor load. The acceleration of OPUS codec allows processing of a greater number of audio channels in the SoC device compared to running the codec entirely on the processor.

In this paper, we present a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. Specifically, we propose an optimization algorithm that targets the reduction of extra off-chip memory accesses caused by inter-processor communication. This is achieved by increasing the application-wide reuse of data that resides in the scratch-pad memories of processors. Our experimental results obtained on four array-intensive image processing applications indicate that exploiting inter-processor data sharing can reduce the energy-delay product by as much as 33.8% (and 24.3% on average) on a four-processor embedded system. The results also show that the proposed strategy is robust in the sense that it gives consistently good results over a wide range of several architectural parameters.

When trying to improve the execution time of scientific applications using parallelism, two alternatives appear as the most extended: to use explicit message-passing or using a shared address memory space. MPI and OpenMP are nowadays the industrial standards for each alternative. We broach the parallelization of an astrophysics code used to measure various properties of the accretion disk in a black hole. Different parallel approaches have been implemented: pure MPI and OpenMP versions using cyclic and block distributions, a hybrid MPI+OpenMP parallelization and a MPI Master-Slave strategy. A broad computational experience on a ccNUMA SGI Origin 3000 architecture is presented. From the scientific point of view, the most profitable conclusion is the confirmation of the robustness of the technique that the original code implements.KeywordsBlack HoleIteration SpaceLoad ImbalanceBlock DistributionOpenMP ThreadThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

An innovative sliding mode load controller for gas turbine power generators: Design and experimental validation via real-time simulation

The death of urban China

This paper presents the development of real-time power system simulation hardware-in-the-loop (RTPSS HIL) testbed for Coordinated Voltage Control (CVC) system by using OPAL-RT simulator. CVC system is a wide area voltage coordination via adjustment of reactive power control equipment remotely with the aim to obtain optimum voltage profile hence, helps in reduction of system losses. This comprehensive lab-scale CVC system testing platform have been designed to validate the CVC system performance under full control of devices in completely safe and controlled environment. Under this testbed, CVC system is tested with various grid condition and contingencies in order to verify the CVC system adaptation and response towards the power system changes hence, able to provide control action and meet its objective function to minimize system losses. The test case also have been simulated in real-time for 24 hours thus as the result, advantages of testing CVC system application in real-time simulation environment is realized as it is able to mimic the actual implementation in the power grid.

Semi-physical simulation technology is a test means and technical tool which is widely used in the process of verifying the feasibility of the designed scheme and the function of the whole system in satellite attitude and orbit control system. In this paper, a scheme of autonomous navigation semi-physical simulation system based on multi-target optical sensor is designed. On this basis, a real-time semi-physical simulation system which is oriented to the on-orbit autonomous navigation task of high-orbit satellite and combined with sensors by hardware platform is established, with xPC Target as the real-time simulation environment, and on-board computer simulator as the carrier of navigation algorithm. The experimental results show that the simulation platform can meet the expected requirements and has good scalability, which can provide experimental environment support for the feasibility verification of other navigation systems.

To incorporate at least the first-order effects of rotor-ship coupling into the existing real- time flight simulation system, a series of CFD computations have been conducted for the ship alone, the rotor alone, and the two together using an actuator disk to represent the rotor. The first-order effects of rotor-ship coupling are obtained by subtracting the rotor alone and the ship alone solutions from the coupled solutions. To further utilize those CFD solutions in a real-time simulation environment, a reduced-order model of rotor-ship coupling effects has been constructed from the above CFD solution database by using Proper Orthogonal Decomposition and Multi-layer perceptrons Neural Network methods. While the solutions of this reduced-order model are in good agreement with the original CFD solutions, running this reduced-order model on a regular PC only takes several milliseconds, satisfying the requirement of a real-time simulation.

Extension of the do-mpc Development Framework to Real-time Simulation Studies

A new hardware platform for digital real-time simulation and control applications is introduced which is highly expandable and customizable due to its modular design and flexible, open interfaces. The system is based on digital signal processors (DSPs) and field programmable gate arrays (FPGAs). A detailed description of the processor and interface boards as core components of the system is given. A small-scale desktop system for hardware-in-the-loop real-time simulations is shown. Furthermore, modeling methodologies and commonly used integration techniques with regard to usual problems and practical implementation are presented. An actual implementation is presented as an example simulation which is used to verify the functionality and evaluate the performance of the real-time simulation platform. A real-time simulation of a buck converter with a time-step of 1 µs without FPGA co-processing is shown and the simulation results are compared to real hardware measurements. To address the common problem of inter time-step switching, solutions are discussed and two approaches are implemented and compared. In total, this paper presents a short overview of digital real-time simulation including modeling and integration, software implementation, hardware platform for code execution and hardware-in-the-loop testing.