Markov Chain-Based Adaptive Scheduling in Software Transactional Memory

Software Transactional Memory (STM) systems provide an easy to use programming model for concurrent code and have been found suitable for parallelizing many applications providing performance gains with minimal programmer effort. With increasing core counts on modern processors one would expect increasing benefits. However, we observe that running STM applications on higher core counts is sometimes, in fact, detrimental to performance. This is due to the larger number of conflicts that arise with a larger number of parallel cores. As the number of cores available on processors steadily rise, a larger number of applications are beginning to exhibit these characteristics. In this paper we propose a novel dynamic concurrency control technique which can significantly improve performance (up to 50%) as well as resource utilization (up to 85%) for these applications at higher core counts. Our technique uses ideas borrowed from TCP's network congestion control algorithm and uses self-induced concurrency fluctuations to dynamically monitor and match varying concurrency levels in applications while minimizing global synchronization. Our flux-based feedback-driven concurrency control technique is capable of fully recovering the performance of the best statically chosen concurrency specification (as chosen by an oracle) regardless of the initial specification for several real world applications. Further, our technique can actually improve upon the performance of the oracle chosen specification by more than 10% for certain applications through dynamic adaptation to available parallelism. We demonstrate our approach on the STAMP benchmark suite while reporting significant performance and resource utilization benefits. We also demonstrate significantly better performance when comparing against state of the art concurrency control and scheduling techniques. Further, our technique is programmer friendly as it requires no changes to application code and no offline phases.

Previous studies in software transactional memory mostly focused on reducing the overhead of transactional read and write operations. In this article, we introduce transaction coalescing , a profile-guided compiler optimization technique that attempts to reduce the overheads of starting and committing a transaction by merging two or more small transactions into one large transaction. We develop a profiling tool and a transaction coalescing heuristic to identify candidate transactions suitable for coalescing. We implement a compiler extension to automatically merge the candidate transactions at the compile time. We evaluate the effectiveness of our technique using the hash table micro-benchmark and the STAMP benchmark suite. Transaction coalescing improves the performance of the hash table significantly and the performance of Vacation and SSCA2 benchmarks by 19.4% and 36.4%, respectively, when running with 12 threads.

Deterministic execution of a multithreaded application guarantees the same output as long as the application runs with the same input parameters. Determinism helps a programmer to test and debug an application and to provide fault-tolerance in the systems based on replicas. Additionally, Transactional Memory (TM) greatly simplifies development of multithreaded applications where applications use transactions (instead of locks) as a concurrency control mechanism to synchronize accesses to shared memory. However, deterministic systems proposed so far are not TM-aware. They violate the main properties of TM (atomicity, consistency and isolation of transactions), and execute TM applications incorrectly. In this paper, we present DeTrans, a runtime system for deterministic execution of multithreaded TM applications. DeTrans executes TM applications deterministically, it executes nontransactional code serially in round-robin order, and transactional code in parallel. Also, we show how DeTrans works with both eager and lazy software TM. We compare DeTrans with Dthreads, a state-of-the-art deterministic execution system. Unlike Dthreads, DeTrans does not use memory protection hardware nor facilities of the underlying operating system (OS) to execute multithreaded applications deterministically. DeTrans uses properties of software TM to ensure deterministic execution. We evaluate DeTrans using the STAMP benchmark suite and we compare DeTrans and Dthreads performance costs. DeTrans incurs less overhead because threads execute in the same address space without any OS system calls overhead. According to our results, DeTrans is 3.99x, 3.39x, 2.44x faster on average than Dthreads for 2, 4 and 8 threads, respectively.

Adaptive policies for multi-mode project scheduling under uncertainty

Transactional Memory (TM) has gained momentum mainly due to its ability to provide synchronization transparency in parallel programs. In transactional applications, accesses to the shared data structures are handles by TM layer with no intervention by a programmer. Time-based software transactional memories (STMs) exploit a global clock to validate transactional data. Unfortunately, the clock becomes a bottleneck especially in programs with large number of concurrent transactions. In this paper, we exploit hardware support to implement the global clock. The hardware clock is implemented on the processor chip and enables bottleneck-free transactional memory run-time systems. Our evaluation using Gem5 simulator shows that the hardware clock is effective and reduces execution time of Stamp benchmarks up to 62%.

Coarse-grained reconfigurable architectures (CGRAs) are increasingly employed as domain-specific accelerators due to their efficiency and flexibility. However, the existing CGRA architectures suffer from low hardware resource utilization and performance due to the limitations of the scheduling scheme. In this article, an adaptive scheduler (denoted as DPTM) for concurrent and multi-task interleaved pipelining-oriented CGRA is introduced, which exploits timeslot matching and release methods to avoid the pipeline conflicts and improve the scheduling performance. The characteristics of task scheduling based on directed acyclic graph (DAG) are analyzed, and several performance-influencing factors are extracted to build a scheduling performance model for reducing the time cost of scheduling and guiding the design of scheduling schemes. Moreover, the scoreboard method of dynamic instruction schedulers is optimized to control the entry time of multiple tasks into the pipeline, and then a timeslot matching method is proposed to provide non-conflict pipelining for the multiple tasks. Further, a timeslot release method is presented to release the timeslots for unscheduled sub-tasks dynamically, which can adapt the parallel processing of multiple tasks and decrease the scheduling time. Then, an adaptive scheduling scheme combines the dynamic priority-based task assignment method, timeslot matching method, and timeslot release method to schedule massive tasks for CGRA. Finally, the overall architecture of DPTM is introduced and designed to validate the efficacy of the proposed scheduling scheme. Experimental results show that the proposed timeslot matching/release approach reduces 84% total scheduling time and decreases 40% average scheduling time at most compared to the non-timeslot-matching scheduling schemes, the proposed task assignment approach decreases 8% total scheduling time and lowers 3% average scheduling time compared to the existing approaches, and the proposed scheduler decreases 51% critical path delay, lowers 35% area overhead, and reduces 12% power consumption at most compared with the existing schedulers.

To meet the expected performance, future exascale systems will require programmers to increase the level of parallelism of their applications. Novel programming models simplify parallel programming at the cost of increasing runtime overheard. Assisted execution models have the potential of reducing this overhead but they generally also reduce processor utilization.We propose an integrated hardware/software solution that automatically partition hardware resources between application and auxiliary threads. Each system level performs well-defined tasks efficiently: 1) the runtime system is enriched with a mechanism that automatically detects computing power requirements of running threads and drives the hardware actuators; 2) the hardware enforces dynamic resource partitioning; 3) the operating system provides an efficient interface between the runtime system and the hardware resource allocation mechanism. As a test case, we apply this adaptive approach to STM2, an software transactional memory system that implements the assisted execution model.We evaluate the proposed adaptive solution on an IBM POWER7 system using Eigenbench and STAMP benchmark suite. Results show that our approach performs equal or better than the original STM2 and achieves up to 65% and 86% performance improvement for Eigenbench and STAMP applications, respectively.

Fuzzy rule generation for adaptive scheduling in a dynamic manufacturing environment

With the development of multimedia Web sites and increasingly diversified services, there is a growing demand for different levels of quality of service (QoS) on scalable Web servers to meet changing resource availability and to satisfy different client requirement. Most Web servers in practical use a queuing policy based on the best effort model, which employs the first-come-first-service (FCFS). In this paper, a Web QoS control strategy that is proposed is based on the session, the content of the request and the user's privilege. According to the session, content of the request and the user's privilege, the customers can be classified into different classes. An adaptive priority scheduling policy is also proposed to change the order of server process request. We conduct simulation experiments and compare the QoS performance of these scheduling rules with the FCFS scheme. The simulation results demonstrate better QoS performance using this strategy when requested services exceed the capacity of a Web server.

Increasing demands for multimedia networking ser- vices will require a much larger bandwidth than what is com- monly available today. Thus, optical medium, which offers a usable bandwidth of the order of Terahertz, is chosen for high- speed local and metropolitan area networks. However, the nodal electronic interfaces cannot cope up with this enormous channel rate of the optical medium. To solve this incompatibility problem, multiple channels are often derived from the optical medium by using wavelength division multiplexing (WDM). Each of these channels has a smaller bandwidth and can be accessed by elec- tronic interfaces. In this paper, we investigate an efficient and fair access scheme, called FairNet, by which a number of parallel channels can be shared among a number of nodes, connected by an optical bus-based structure. The network consists of AT nodes and W parallel channels. All the channels are slotted and synchronized and the slot length equals the packet transmission time. Since high-speed interfaces are expensive and since optical signal strength reduces with the number of taps, only a small number of transmitters and receivers are used. Specifically, each node is equipped with 1) a tunable transmitter which can be tuned to any of the IV channels, 2) a fixed receiver which can receive from a preassigned channel, and 3) a tunable sensor. Network operating parameters for various fairness criteria (e.g., equal average packet delay at each node) are analytically obtained using both exact and approximate approaches. Also, to adapt to the fluctuations (if any) of the offered loads at various nodes, the transmission probabilities can be dynamically adjusted.

This paper presents an approach for adaptive scheduling and robustness optimization in global logistics networks by integrating multimodal deep reinforcement learning with Internet of Things (IoT) technologies. We propose an integrated framework comprising a multimodal data fusion mechanism that synthesizes heterogeneous IoT sensor data, historical records, and contextual information; an adaptive deep reinforcement learning architecture that generates dynamic scheduling policies; and a multi-objective robust optimization method that balances operational efficiency with system resilience. The framework addresses key challenges in global logistics including demand volatility, transportation disruptions, and environmental uncertainties. Comprehensive experiments conducted on real-world logistics datasets demonstrate that our approach outperforms traditional methods with an 18.7% reduction in operational costs, 12.4% improvement in service levels, and significantly enhanced robustness under various disruption scenarios. The proposed method maintains 83% performance stability during complex disruptions compared to 51–72% for alternative approaches, while keeping computational requirements feasible for practical deployment. This research demonstrates potential contributions to AI-driven logistics operations management by showing improved supply chain performance through multimodal learning and robust optimization techniques.

The problem of optimal scheduling of multicast traffic in time-varying wireless networks is studied in the framework of utility maximization. Since the wireless channel cannot be known exactly, only scheduling policies that take decisions based on a possibly inaccurate estimate of the wireless channel state are considered. A stationary, on-line, gradient-based scheduling and rate control policy is introduced which identifies at every decision instant the sources that should access the wireless medium along with their respective transmission rates. Furthermore, in the case that more than one optimal rate allocation is possible, the one that requires the minimum sum-power expenditure is selected by the policy. The optimality of the proposed policy among all policies that have access to the same estimate of the current wireless channel state is established through stochastic approximation arguments.

Modern-day healthcare is being challenged by the critical nature of traffic requirements for services like health monitoring, remote consultations, and robotic surgery. While the existing literature addresses various algorithms for real-world throughput prediction, there is a lack of systematic exploration of these algorithms in healthcare. In this paper, we study the problem of accurately predicting performance parameters in a smart healthcare environment. Taking into account the characteristics of healthcare networks, we compare machine learning based algorithms and prediction models for performance and performance characteristics. We designed a model based on the Healthcare 4.0 paradigm for throughput prediction of two different types of healthcare data - sensor data used for telemonitoring e.g., Blood Pressure (BP) and Sp02 sensor data, and audio/video data that is used for teleconsultation. Among the algorithms, K-means performs the best achieving 72.68% accuracy and 75.9% sensitivity, while Naive Bayes gives better precision at 72% in predicting the throughput.

In recent software transactional memory proposals, a contention manager module is responsible for ensuring that the system as a whole makes progress. A number of contention manager algorithms have been proposed and empirically evaluated.In this paper we lay some foundations for a theory of contention management. We present the greedy contention manager, the first to combine non-trivial provable properties with good practical performance.In a model where transaction delays are finite, the greedy manager guarantees that every transaction commits within a bounded time, and the time to complete n concurrent transactions that share s objects is within a factor of s(s+1)/2 of the time that would have been taken by an optimal off-line list scheduler. No contention manager reviewed in the literature satisfies both the properties. Benchmark results convey our claim of the practicality of the greedy manager.

Transactional memory is a high-level programming abstraction for synchronizing concurrent tasks investigated in different architectures, such as multicores, distributed systems and GPUs. Software transactional memory systems (STMs), including those for GPUs, are usually implemented using a lock-based system, where the locks that protect memory locations being accessed by a transaction are acquired, either at commit time or during transaction execution, to guarantee the atomicity of the transaction’s changes to memory. Transactional memory systems can also be lock-free or obstruction-free. Still, such STM algorithms are complex to implement in languages that do not support garbage collection, as they rely on a structure called locator, which must be used to acquire ownership of transactional objects. Every time a transaction needs to access an object in write mode, a new locator is created to substitute the current locator of the object. As transactions can be aborted at any time, and concurrent transactions must read the locators of objects to access their current versions, it is difficult to know when exactly such a locator is not being used and can be freed, a common problem in designing lock-free data structures. This paper presents OFG-STM, an STM system for GPUs inspired by obstruction-free STM algorithms. OFG-STM takes advantage of the fact that GPU threads executing the same kernel execute the same code, and threads in a warp execute a kernel in lockstep, to introduce a garbage-collection phase every time a number of transactions has committed. This paper presents the design and implementation of the OFG-STM system, as well as experiments demonstrating its usability.