Maskless Patterning of Low-Temperature High-Mobility ZnO

With the expansion of the semiconductor supply chain, the use of recycled field-programmable gate arrays (FPGAs) has become a serious concern. Several methods for detecting recycled FPGAs by analyzing the ring oscillator (RO) frequencies have been proposed; however, most assume the known fresh FPGAs (KFFs) as the training data in machine-learning-based classification. In this study, we propose a novel recycled FPGA detection method based on an unsupervised anomaly detection scheme when there are few or no KFFs available. As the RO frequencies in the neighboring logic blocks on an FPGA are similar because of systematic process variation, our method compares the RO frequencies and does not require KFFs. The proposed method efficiently identifies recycled FPGAs through outlier detection using direct density ratio estimation. Experiments using Xilinx Artix-7 FPGAs demonstrate that the proposed method successfully distinguishes recycled FPGAs from 35 fresh FPGAs. In contrast, a conventional recycled FPGA detection method results in certain misclassification.

A CMOS three-stage ring oscillator is examined in UMC 0.18µm technology. The influence of resistor and PMOS transistor, as inverter feedbacks, on the ring oscillator frequency and the peak-to-peak amplitude is investigated. Simulation results showed that by varying the feedback transistor control voltage from 0 to V dd , the ring oscillating frequency can be controlled in the range of 1.46 GHz for the three PMOS transistor feedbacks topology, 0.86 GHz in the two feedbacks architecture, and 0.36 GHz (the best case) in the one feedback ring oscillator design. In the case of ring oscillator design with three resistive feedbacks, the working frequency is decreased from 5.6 GHz to 3.92 GHz, for the resistance changes from 0.5 kΩ to 4 kΩ. Moreover, the maximum frequency obtained in the latter case is significantly higher than 3.77 GHz achieved without any feedback.

In FPGA, routing hotspot affects ring oscillator (RO) performance. The significant difference in routing hotspot between RO locations eliminates physical variation, which is the identity of Physical Unclonable Functions (PUF). This study compares the performance of conventional and uniform routing hotspot RO in Cyclone V chips. For this purpose, ROs and counters are placed in 10 adjacent locations. RO frequency at all locations was measured by a Digital Discovery II, a PC based logic analyzer. In the conventional design, there are significant differences in routing hotspot among RO locations. Meanwhile, in a uniform design, the difference in routing hotspot has been reduced by relocating several logics around specific locations. As a result, the reliability of the conventional design is higher than the uniform routing hotspot design when implemented with 11-stage RO (RO11) and 20-stage RO (RO20). However, the uniqueness of the uniform routing hotspot is better than the conventional ones. Furthermore, the uniformity of the uniform routing hotspot design is closer to the ideal in 20-stage. Conversely, in the 11-stage implementation, the closer uniformity to the ideal is obtained using a conventional design.

This paper deals with the design and analysis of the frequency of ring oscillators using the CMOS 45nm, 32nm, 22nm in a Symica simulation tool. A Ring Oscillator is an effective device made up of an odd number of NOT gates and its output runs between two levels of power standing up and down. There are many challenges ahead while designing a CMOS ring oscillator that can be delay, sound, and glitches. CMOS is the technology of choice for several applications, low-power CMOS oscillators are in high demand. The frequency of a CMOS ring oscillator was measured using waveform time zones for five, seven, and nine phases. This aids in the comparison of ring oscillators at various technology nodes and it is observed that the frequency is found to be maximum at a five-stage ring oscillator in each case i.e. 12.97GHz at 45 nm, 8.25GHz at 32 nm, 4.74GHz at 22 nm.

The article considers a bipolar field-effect (BiFET) test chip, designed to measure volt-ampere characteristics (VAC) of active and passive integrated elements, as well as the frequency of ring oscillators (RO) at cryogenic temperatures. The feature of the RO is the implementation of frequency-assigning capacitors on p-n-junctions of the transistors under study. A method for identifying the temperature coefficients of Spice-parameters based on VAC measurements of the RO elements and frequency is described.

A novel built-in self-test (BIST) algorithm has been devised in this work. The concept of the algorithm is that process variation within a die is usually location based; it is not random. Therefore, if a low frequency ring oscillator is placed 40μm away from the transistors in an 80 GHz low noise amplifier (LNA), both the LNA and the ring oscillator undergo similar process variation in device sizes. Device variation in the ring oscillator can be predicted from it's oscillation frequency shift. It is assumed that the amplifier's device also vary in similar fashion. Thus, from a low frequency measurement of the ring oscillator's frequency, the device variation in the high frequency amplifier can be estimated. This reduces the cost of high frequency measurements. The work is demonstrated in Advanced Design System (ADS) simulation.

Physical Unclonable Functions (PUF) are an emerging hardware security primitives proposed by various researchers in last one decade. PUFs are useful security architectures used for identification, authentication and cryptographic key generation. Many PUF topologies are proposed in the past targeting both ASIC and FPGA. It is nearly impossible to get two PUF circuits with same characteristics for the same design. PUFs make use of random process variation occurring during manufacturing of IC which is uncontrollable. The most versatile PUF is ring oscillator (RO) PUF, in which the frequencies of ring oscillators are compared to produce the PUF response. The conventional approach consumes large number of ring oscillators and requires all RO's to be mutually symmetric. In this paper, we have proposed a RO-PUF for FPGA devices, which is capable of generating multiple output bits from each ring oscillator with better security metrics in comparison with PUF designed with similar technique. The PUF is implemented on Xilinx Spartan 3E FPGA boards and the challenge-response pairs (CRP) are verified for statistical properties.

The reliability of integrated circuits (ICs) is a growing concern with modern electronics. Between the complex design and manufacturing processes of ICs, designs are susceptible to being tampered with, counterfeited, or manufactured with a compromised process technology. This can lead to accelerated aging and shorter lifespans of ICs. In this paper, we propose a light-weight machine learning-based method for approximating future ring oscillator values for aging anomaly detection. Our method relies on an LSTM neural network to predict future ring oscillator frequencies on an FPGA. This prediction is then compared with the measured frequencies to ensure proper aging and reliability of the FPGA. We demonstrate that an increase in the prediction error of ring oscillator frequencies over time shows that there is additional hardware active on the FPGA, i.e., a hardware trojan is present.

Prediction of variation aware FOSC in ring oscillators (ROs) to mitigate the impact of aging on RO-PUF

Logic gates serve as the fundamental building blocks of digital circuits, and among them, the XOR (exclusive OR) gate stands out due to its unique properties. The XOR gate outputs true only when the number of true inputs is odd, making it a pivotal element in various applications, especially in the realm of machine learning and AI development. Korean studies at the intersection of digital logic and recreational mathematics have demonstrated how XOR gate principles provide an effective framework for algorithmically solving the Lights Out game. Comparative research conducted in Korea indicates that the puzzle-solving mechanics of the Lights Out game can be effectively analyzed using the same principles that govern XOR gate behavior in digital circuits. We explore how linear algebra can be used to analyze the Lights Out game. The XOR gate can also be used in AI development in several contexts, particularly in areas that involve binary decision-making, error detection, and encryption/decryption. Simple computations, reversibility, symmetry, and inversion are some of the useful properties of the XOR gate, which make the XOR gate versatile, popular, and applicable across all binary data.

Plasma-induced damage (PID) and bias temperature instability (BTI) are inevitable reliability issues that degrade the performance of transistors. In this study, PID and BTI, depending on the type of antenna layer, are evaluated in current-starved ring oscillators (ROs) to separate degradations in PMOS and NMOS transistors in a 65 nm silicon-on-insulator (SOI) process. Oscillation frequencies of ROs fluctuate with the performance of MOSFET switches between power/ground rails and virtual power/ground nodes. The initial frequencies of ROs with PMOS switches having antennas on upper layers decrease. However, those with NMOS switches become higher than those without PID because high-k dielectrics are damaged by positive charges. The degradation induced by negative BTI (NBTI) in PMOS is 1.5 times larger than that induced by positive BTI (PBTI) in NMOS. However, both NBTI- and PBTI-induced degradations are the same among different antenna layers. The frequency fluctuation caused by PID is converted to threshold voltage shifts by circuit simulations. Threshold voltages shift by 8.4 and 11% owing to PID in PMOS and NMOS transistors, respectively.

In this paper, a new Physically Unclonable Function (PUF) has been implemented and tested. The idea behind this PUF is to compare the bias of the same Galois ring oscillator implemented in different locations within the FPGA. The implemented PUF has been compared to a Ring Oscillator PUF in terms of reproducibility, random-like response and uniqueness. Furthermore, the spatial correlation of the bias of the Galois oscillators has been studied and compared to the spatial correlation of the frequency of regular ring oscillators.

Design Rule Checker (DRC) is one of the most important tools of modern VLSI layout design. DRC involves the checking of design rules in a VLSI layout. In recent developments of chips with an even lower channel length of the transistor, the number of DRC violations has increased from a few hundred to thousands, thus checking so many DRC violations has become a critical point in the layout generation of custom circuits. Many industries came up with different approaches to tackle this problem and to make the DRC forming and checking stage faster. Since the evolution of Machine Learning, researchers from every field of engineering & even from management are relying on various machine learning algorithms to make existing processes faster and more accurate. This paper is aimed in the same direction, which is to implement a machine-learning algorithm to make the DRC checking and execution process faster and more accurate concerning existing processes. This paper is aimed to propose a different approach to implement DRC which is based on Convolutional Neural Network (CNN) model technique. The layout violations in the circuit will be detected by our trained CNN Model, specially trained for some specific layout violations in a circuit. The proposed model is successful in the detection of the design rule constraints in a layout with an accuracy of 98% and can be expanded to larger and more complex layouts. The current scope of this paper includes hundreds of layouts for 3 different logic circuits and the accuracy obtained is quite encouraging.

In the beginning, there were no design rules. Experts handling IC design and process development were knowledgeable in both disciplines. As circuit variety and complexity increased, a division of labor became necessary during the early 1970s. Since then, design rules have regulated the design-manufacture interface. These rules represent a compromise between designers, who often desire small, densely packed transistors and circuit elements, and manufacturers, who are concerned with high-yielding processes. Circuit models such as Spice parameters for electrical simulation, and geometrical description formats such as Gerber Data Stream II (GDSII) and Caltech Intermediate Form (CIF), complement design rules and serve as a common language between designers and manufacturers. When a layout - the geometrical shapes that collectively describe a circuit - adheres to all design rules, the fabricated circuit functions according to the design. This article provides a clear view of two complementary approaches to managing the increasingly complex design-manufacturing interface, restricted design rules and model-based design. The author's straightforward discussion is very timely as our industry is moving forward combining both approaches.

The generation of random numbers is crucial for practical implementations of cryptographic algorithms. In this sense, hardware security modules (HSMs) include true random number generators (TRNGs) implemented in hardware to achieve good random number generation. In the case of cryptographic algorithms implemented on FPGAs, the hardware implementation of RNGs is limited to the programmable cells in the device. Among the different proposals to obtain sources of entropy and process them to implement TRNGs, those based in ring oscillators (ROs), operating in parallel and combined with XOR gates, present good statistical properties at the cost of high area requirements. In this paper, these TRNGs are revisited, showing a method for area optimization independently of the FPGA technology used. Experimental results show that three ring oscillators requiring only three LUTs are enough to build a TRNG on Artix 7 devices from Xilinx with a throughput of 33.3 Kbps, which passes NIST tests. A throughput of 50 Kbps can be achieved with four ring oscillators, also requiring three LUTs in Artix 7 devices, while 100 Kbps can be achieved using an structure with four ring oscillators requiring seven LUTs.