Maude- based design space exploration of embedded systems

This paper introduces a cooperative service composition language called CCML which aims to facilitate the description of services, their interfaces and their behavior, further to reduce the complexity required to compose services. Interaction rules among services rely on a cooperative computation model, i.e. KPN (Kahn Process Network), which adopts dataflow and channel based asynchronous communication pattern among process nodes. Formal model for behavioral semantics of CCML is based on CCS process algebra which presents a high expressive power, capable of capturing CCML behavioral semantics. We give an operational semantics to CCML in the form of a labeled transition system (LTS) and describe the events of a LTS associated to the main CCML constructs, which are sequence, condition, loop and parallel. Finally, we present an application case to show how to describe service composition using CCML

Typical design flows supporting the software development for multiprocessor systems are based on a board support package and high-level programming interfaces. These software design flows fail to support critical design activities, such as design space exploration or software synthesis. One can observe, however, that design flows based on a formal model of computation can overcome these limitations. In this article, we analyze the major challenges in multiprocessor software development and present a taxonomy of software design flows based on this analysis. Afterwards, we focus on design flows based on the Kahn process network (KPN) model of computation and elaborate on corresponding design automation techniques. We argue that the productivity of software developers and the quality of designs could be considerably increased by making use of these techniques.

In this paper, we present a reconfigurable system on chip design framework that generates an architectural design along with binding and scheduling algorithm, specific to the input application in Kahn Process Network specification.The likelihood that tasks and communication channels may have many potential physical manifestations is explicitly recognised and embraced, to assist the design exploration process. The architectural design, binding and scheduling problems are formulated as a Integer Linear Programming problem, with physical constraints such as available logic resources, computation time and memory footprints to guide the design space exploration.

Currently, embedded systems make use of large, multiprocessing systems on chip integrating complex application software running on the different processors in close interaction with the application-specific hardware. These systems demand new modeling, simulation, and performance estimation tools and methodologies for system architecture evaluation and design exploration. Recently approved as IEEE 1666 standard, SystemC has proven to be a powerful language for system modeling and simulation. In this chapter, SCoPE, a SystemC framework for platform modeling, SW source-code behavioral simulation and performance estimation of embedded systems is presented. Using SCoPE, the application SW running on the different processors of the platform can be simulated efficiently in close interaction with the rest of the platform components. In this way, fast and sufficiently accurate performance metrics are obtained for design-space exploration.

OPAL-RT enables the simulation of large-scale, complex systems efficiently. Systems that would typically require hours or even days to simulate on a conventional personal computer can be executed in real time using OPAL-RT, with time steps in the microsecond or nanosecond range. High performance, flexibility, and low entry-level cost are key attributes of the OPAL-RT platform. The OPAL-RT real-time simulation platform is an advanced model-based engineering design and testing environment. It delivers outstanding real-time performance for experimental studies and is widely used in engineering design applications. Therefore, it is essential to examine its hardware architecture, software structure, and real-time performance in detail. A comprehensive understanding of its hardware and software architecture, along with its simulation process, provides a structured overview of the platform. Furthermore, the application of OPAL-RT in electrical power systems serves as a valuable reference for microgrid, smart grid, and other real-time system implementations

Large-scale battery systems have been applied to a number of grid-level energy storage services such as microgrid capability and distribution upgrade due to the penetration of solar/wind energy. In these battery applications, charge imbalance among battery cells/modules/packs becomes a common issue, which can reduce available battery capacity, accelerate battery degradation, and even cause some safety hazards. To tackle this issue, various battery charge equalization (BCE) systems have been proposed in recent decades, among which the module-based BCE system is widely viewed as a promising solution and has drawn increasing attention. In this paper, we study the module-based BCE systems by presenting a mathematical model that can characterize the charge transfer behavior in such systems, and then proposes computationally efficient algorithms to estimate the instantaneous battery cell state of charge (SOC), charge equalization time, and charging/discharging time, based on given system parameters and various initial battery cell SOCs. In addition, the conditions are derived to ensure that all battery cells can reach charge equalization and then get fully charged/discharged together without overcharging/overdischarging. All theoretical results are illustrated and justified through extensive numerical experiments.

Hardware/Software (HW/SW) partitioning is becoming an increasingly crucial step in embedded system co-design. To cope with roughly assumed parameters in system specification and imprecise benchmarks for judging the solution's quality, researchers have been trying to find methods for a semi-optimal partitioning scheme in HW/SW partitioning for years. This paper proposes an application of a hybrid neural fuzzy system incorporating Boltzmann machine to the HW/SW partitioning problem. The hybrid neural fuzzy system's architecture and performance estimation against simulated annealing algorithm are evaluated. The simulation result shows the proposed system outperforms other algorithm in cost and performance.

This paper presents an adaptive e-learning system which supports collaborative learning based on a location-based social network and semantic modeling. In the system, a social network among e-learning learners is dynamically constructed on the basis of the location information of learners using GPS sensors for collaborative learning. In addition, user modeling for semantic social network and adaptive e-learning is supported. For these, a mechanism that supports the construction of a dynamic social network using the location information of smart phones is provided. The user modeling for the construction of a semantic social network and the support of adaptive e-learning considers the information such as the users' achievement, preference, and learning goal. Through this system, e-learners can find mentors who are able to facilitate their learning and create communities for collaborative learning offline and online. The support of a location-based social network service and semantic user model in our system would increase interactions among e-learners and improve satisfaction regarding their mobile learning environment.

The attenuation rate of the ground wave signal with range is a factor limiting the performance of coastal radars. We show that observed attenuation rates are less than theoretically predicted rates at 25 MHz. This result, contrary to earlier findings at lower frequencies, suggests the onset of tropospheric ducting above 20 MHz. The attenuation rates for various sea states and distances are tabulated to allow estimates of system performance near 25 MHz.

As the need for personal authentication increases, many people are turning to biometric authentication as an alternative to traditional security devices. Concurrently, users and vendors of biometric authentication systems are searching for methods to establish system performance. This paper presents a model that defines the parameters necessary to estimate the performance of fingerprint-authentication systems without going through the rigors of intensive system testing inherent in establishing error rates. The model presented here was developed to predict the performance of the pore-based automated fingerprint-matching routine developed internally in the research and development division at the National Security Agency. This paper also discusses the statistics of fingerprint pores and the efficacy of using pores in addition to the traditionally used minutiae to improve system performance. In addition this paper links together the realms of automated matching and statistical evaluations of fingerprint features. The results of this link provides knowledge of practical performance limits of any automated matching routine that utilizes pores or minutia features.

In this paper, a distributed algorithm for localization and tracking in wireless sensor network is designed and implemented. Combining the fingerprint approach and subgradient optimization, the proposed algorithm, called golf algorithm, uses different strategies to attain fast movement for tracking a moving object and a fine tune to approach a stationary object, like a drive and a putt on the putting green in the golf. Based on the WLS objective function, a recursive form for both the fingerprint approach and subgradient optimization is derived and can be accomplished by anchor nodes in collaboration. From simulation results, we can see the proposed algorithm has better estimation performance than the conventional decentralized algorithms to localize a stationary or moving target in large wireless sensor networks. In addition, its hardware architecture is designed. The CORDIC operation is employed to compute the vector norm. Parallel processing is used to handle the calculation of fingerprint data. The tracking trajectories of the floating-point program and fixed-point hardware implementation are shown to be quite similar with small finite precision effect, which verifies the feasibility of this hardware solution.

A data flow image pipelined processor VLSI chip (ImPP:µPD7281) has been developed. Its hardware architecture and the experimental Template Controlled Image Processing System -3 (TIP-3), which includes 8 ImPP chips, are described. The ImPP is characterized by its data flow architecture and flexible pipeline processing. The ImPP has a uni-directional pipeline bus. The connection between ImPPs is easy and does not require extra circuits. The processing performance can be increased by connecting many chips to each other. In this multiple ImPP configuration, individual ImPPs share different portions of the pipeline programs and different portions of spatial data. The ImPP can be used in various system configurations. A single ImPP chip is sufficient for simple processing and multiple ImPPs are useful for a faster image processing system. Performance estimation using a software simulator, and also using an actual hardware system has been carried out. TIP-3's top performance is 40 MIPS. The main factors which influence execution efficiency are discussed and analyzed.

An M-ary decision feedback communication system with the MAP strategy is investigated. The performance of this system is analytically evaluated as follows. First, an approximate lower performance bound is found by means of the Cauchy inequality. Then an approximate lower performance bound is found by means of the Jensen inequality. Finally, the bounds are compared and found to coincide, yielding an approximate estimate of the system performance. The same estimate may also be obtained by means of mean path approximation. Thus, the mean path approximation tends to underestimate the system average transmission time. For verification purposes, the results are compared with those obtained from computer simulation and are found to be in good agreement. Furthermore, the feedback transmission is compared with one-way transmission. It is shown that feedback systems are better than one-way systems in terms of the signal/noise ratio required to achieve a prescribed error probability. The estimated power advantage of feedback systems is between 5.4 dB and 3 dB, depending on the number of possible signals M; the power advantage decreases as M increases. The results obtained for M→ ∞ imply that the feedback increases the capacity of an infinite-bandwidth Gaussian channel. However, the last result was not proved with the degree of rigour required in mathematics; rather, we have used approximate performance bounds and computer simulation data in our analysis.

10 - Cooling Towers

Automated Design Space Exploration (DSE) is a critical part of system-level design. It relies on performance estimation to evaluate design alternatives. However, since a plethora of design alternatives need to be compared, the run-time of performance estimation itself may pose a bottleneck. In DSE, fastest performance estimation is of essence while some accuracy may be sacrificed. Fast estimation can be realised through capturing application demand, as well as Processing Element (PE) supply (later on called weight table) in a matrix each. Then, performance estimation (retargeting) is reduced to a matrix multiplication. However, defining the weight table from a data sheet is impractical due to the multitude of (micro-) architecture aspects.