Maximum Pipelining Of Array Computation: A Pipelined Code Mapping Scheme For Dataflow Computers

Most computer architecture courses are geared toward the classical von Neumann style of computer architectures, mentioning only in passing other models such as data flow computation. This is unfortunate, due to the high degree of parallelism possible using data flow. We present an alternative course, designed as an elective in computer architecture for upper level undergraduate or graduate students, that presents a side-by-side comparison of von Neumann and data flow architectures.Our teaching environment is based on Simple Arithmetic SISAL (SAS), a subset of the applicative programming language SISAL, which we designed for both teaching about and research into data flow architectures. SAS runs in a highly integrated environment, allowing students to implement their program on a von Neumann architecture, then observe its execution through a data flow simulator. The environment runs on a standard IBM-style personal computer, providing a cost-effective platform for presenting the course.

This paper deals with the data flow computing paradigm, with the characteristics of program execution control using a flow of data instead of a flow of instructions. Data flow computing represents an important alternative to the control flow computing paradigm, which is currently the mainstream computing paradigm represented by architectures mostly based on the Von Neumann principles, in which the flow of program execution is controlled by a flow of instructions. This paper also deals with the tile computing paradigm - a modern approach to designing multi-core microprocessors with components laid out in two-dimensional grids with various geometries of cores, memory elements and interconnection networks with architectures using both data flow and control flow program execution control. In this paper we introduce a data flow computer architecture designed at the Department of Computers and Informatics, Faculty of Electrical Engineering and Informatics, Technical University of Kosice, Slovakia, employing the principles of tile computing. Efficient data flow architectures applying a different approach to the control of program execution flow also demand a different operating memory design. As the part of our effort to build data flow computer architectures, we have designed an innovative memory architecture that fulfils the specific needs of data flow computer architectures. In the final section of the paper we describe the functions and operations possible with this kind of memory.

This paper presents a cost-effective scheme for partitioning large data flow graphs. Standard data flow machine architectures are assumed in this work. The objective is to reduce the overhead due to token transfers through the communication network of the machine. When this scheme is employed on large graphs, the load distribution on the rings of the data flow machine is also improved. A canonical form of a data flow graph is introduced to establish the relationship between the communication overhead and the size reduction of the partition cut-set. General lower estimates on the overhead are derived in terms of processing and transmission delay parameters of the machine. The method uses heuristics and an evaluation function to guide the partition algorithm. Some implications of the proposed method on the organization of the data flow machines are discussed.

The ULowell Data Flow Project combines dataflow hardware, dataflow software, and a data flow development environment. The hardware component, a data flow coprocessor card, utilizes seven NEC 7281 Image Pipelined Processors. Each chip models a static dataflow computation and is programmable. The coprocessor was designed and implemented by ULowell personnel and uses an AMIGA 2000 as a host. The software component currently consists of a library of data flow image processing algorithms and an evolving software development environment. Currently the image processing library includes typical imaging operations such as: edge enhancement, filtering, histogramming, and affine transformation. The software development environment (SDE) is depicted in Figure 1. The SDE contains a Data Flow Graph Editor which programmers use to design their data flow code. The data flow algorithm can then be converted directly into NEC data flow assembly code which is then assembled using the ULowell Data Flow Assembler. The assembler differs from NEC's assembler in that it can produce relocatable code. The object code output of the assembler is given to the Data Flow Resource Manager. The resource manager monitors the available resources within the chips. Thus, if a single process does not totally utilize a chip's table space or memory, then a second process may be concurrently loaded onto the same chip. The ability to have multiple data flow processes coexisting within a single chip is unique to the ULowell environment. The data flow resource manager can download and monitor code to either the hardware or to a software simulator/debugger. The simulator/debugger can monitor and trace data flow tokens as they proceed through the chip. Output of the simulator/debugger can be fed back into the data flow graph editior to visually trace token flow through the original program design. The last component of our SDE is a High Level Language translator which can compile programs written in SISAL, a high level language for parallel computation, down to NEC 7281 assembly language. We have already implemented the relocatable assembler, and the data flow resource manager. Prototype versions of the high level translator, simulator/debugger and graph/editor are currently being implemented.

A "buildable" dynamic tagged token data flow architecture tailored for small, highly iterative algorithms such as the Mandelbrot set is presented. Historically, dataflow machines have required a major hardware effort to construct. As a result, very few real machines have been built. In contrast to these large scale machines, this project was intended to be built at minimal expense and with "off-the-shelf" parts. A novel insight into the process of executing a dataflow graph is presented. This insight has resulted in a new architecture utilizing a "pseudo-program counter". This scheme allows a significant reduction in the width of the data paths throughout the PE interconnection network. To further reduce the required hardware, the traditional associative matching store has been eliminated in favor of a more brute-force approach that is workable for the class of algorithms considered for execution on this machine.

Computers, as we know them, are disappearing. Instead of stand-alone devices for word processing or browsing the web, computers are rapidly becoming integrated into everything from smart phones and smart meters to autonomous planes, trains, and automobiles. These compute engines are embedded to imbue these objects with intelligence to interact with the world independently, or to provide value-added services to the human-machine interface. The quest for real-time, autonomous intelligent systems requires new architectures that enable software productivity, and still yield high performance, predictable and low-latency execution, with ultra-low power consumption. In particular, power efficiency is essential to support mobility or autonomous operation for long periods of time. The Stillwater KPU is a distributed data flow processor that offers performance/power densities of 50GFlops/Watt @40nm and 100GFlops/Watt @28nm. It supports fine-grain parallel execution of the inherent parallelism of the algorithm. Because the processing elements are data flow machines they do away with the instruction fetch and decode pipeline of a sequential processor. A typical KPU processing element is 60% smaller than an equivalent sequential processor. Finally, the KPU does not require cache hierarchies to reduce memory latency, reducing the die size of a typical system by 50% or more.

Throughout the entire history of computer architecture, the von Neumann model has been the most mainstream model for computer systems architecture. Data flow computer systems are undoubtedly the most well-studied type of non-von Neumann computer architecture. In this paper, from the perspective of the computer architecture development, we analyze the important role that data flow computing thinking has played in both innovation in computer architecture and in the development of computer architecture over time. We first review the thinking behind data flow computing and analyze the limitations it faced in its early stages. Then we analyze two important technologies used in modern CPUs-out-of-order execution and multi-threading technology-that were both developed using data flow computing thinking. We continue to view streaming computing, streaming processor architecture, and modern GPUs through the lens of data flow computing thinking. Further, we analyze how to apply data flow computing thinking to the development of computer systems in the era of big data intelligence. Finally, we summarize the rules of data flow computing thinking and forecast future development trends.

This paper proposes a parallel processing system -Harray- for scientific computations. Data flow computers are expected to obtain the high performance because they can extract parallelism fully from a program. However, they have many problems, such as the difficulty of controlling the sequence of execution. The -Harray- system is an array processor which adapts two levels of control mechanism; data flow execution in each processor and control flow between processors, in order to take full advantage of both mechanisms. A task which is assigned to a processor is called a “macro-block”. Three types of macro-blocking and three types of activation schemes for the macro-block which initiates its execution are introduced in order to attain the high performance. Moreover, a hardware synchronization mechanism is used to reduce synchronization overhead and to gain the liner speedup of the -Harray- system.In this paper, the system architecture of the -Harray- system and its performance evaluation by software simulation are presented.

In this paper, we propose an efficient techniques, called CD translation, to compile a FORTRAN program to a optimized dataflow code. The CD translation generates the dataflow control information from a control flow graph by using the data flow analysis with the branch node operation, and enables to analyze a sequential program with any type of the control structures (e.g. goto statement and irreducible loop) correctly, while the previous method cannot compile a FORTRAN to the dataflow program perfectly. This analysis technique is much worthy of not only the construction of the compiler for dataflow machines but also the analysis technique for the parallelizing compiler because the dataflow program represents all the program dependencies with only data dependencies unifyingly and enables to analyze all the program dependencies identically. Moreover the FORTRAN compiler implementing the CD translation is introduced.Index Termsdataflow machinecompilerdataflow analysisFORTRAN

Reconfigurable computing refers to the notions of configware and flowware. Configware means structural programming, or programming in space to execute computation in space. Flowware means dataflow programming that schedules the data flow for output from or input to the configware architecture. In this paper, data flows of a synthesized computation are formalized. This means that data flow is specified as a behavioral stream function in stream calculus, which is used to underpin the semantics for Register Transfer Level (RTL) synthesis. A stream representation allows the use of coinductive principles in stream calculus. In particular, using the coinductive proof principle, we show that behavioral stream functions in the three-stage synthesis process (scheduling, register allocation and binding, allocation and binding of functional units) are always bisimilar regardless of changes in a scheduling, allocation or binding procedure. Our formalization makes pipelining possible, in which all functional units as well as registers of hardware resources are reused during different control steps (C-steps). Moreover, a coinductive approach to verifying flowware synthesis, which is independent of the heuristic during register allocating and binding step, is proposed as a practical technique.

The paper discusses the shift in the computing paradigm and the programming model for Big Data problems and applications. We compare DataFlow and ControlFlow programming models through their quantity and quality aspects. Big Data problems and applications that are suitable for implementation on DataFlow computers should not be measured using the same measures as ControlFlow computers. We propose a new methodology for benchmarking, which takes into account not only the execution time, but also the power and space, needed to complete the task. Recent research shows that if the TOP500 ranking was based on the new performance measures, DataFlow machines would outperform ControlFlow machines. To support the above claims, we present eight recent implementations of various algorithms using the DataFlow paradigm, which show considerable speed-ups, power reductions and space savings over their implementation using the ControlFlow paradigm.

This paper presents WFSPM, a transferable end-toend predictive maintenance system for autonomous inspection centered on a Mahalanobis-distance (MD) health index (HI). We demonstrate the approach on a percussion-acoustics case study (stator wedge fastener strength) while keeping the architecture sensor- and asset-agnostic. The standards-compliant pipeline (data flow, features, decision rules, UI/reporting) includes adapter endpoints for cell controllers and line dispatchers and maps the MD-HI to a 0-100 scale for field interpretability. WFSPM shows strong static performance and robustness to injected noise, supporting in-cell mobile-manipulator rechecks without retuning thresholds. Scenario-based prognostics and Health Management (PHM) key performance indicators (KPIs) and lead-time analyses quantify an actionable cycle of early warning, action and recovery, with HI/dual-threshold events mappable to manufacturing-cell KPIs. Overall, WFSPM is explainable, robust, and policy-tunable, and transferable to mixed-model manufacturing cells for autonomous inspection.

For common data flow schemes, the number of copies of tokens made during a computation is shown to be a Blum complexity measure.(1) Results from abstract complexity theory (see Ref. 2) then hold for the copy measure, indicating, for example, that any implementation of a data flow processor will be constrained by its ability to copy tokens. The copy measure is a natural measure of complexity for data flow computations, and is distinct from the usual time or space measures. The result is generalized to a wider class of data flow schemas, including those with an apply operator. An example is also given of a data flow scheme which makes no copies.

This paper postulates a novel N-dimension computing machine that operates in an unconventional manner. This postulate aims at solving existing problems in higher dimensions, where one must re-think the scope of a given problem domain beyond the one-dimension Turing machine to dictate all subsequent problem representation, problem transformation, and algorithmic derivation. Two over-simplified well-known problems, namely, the Traveling Salesman Problem and the Tower of Hanoi problem are presented to demonstrate the point. Both synthetic problems are effectively adapted to solve a real world project. To realize the postulate in a viable architectural construct, data flow and molecular computers are investigated since they show potential computation power. Unfortunately, they are still confined to working in one-dimension domain. A biological-like architecture for software systems is proposed in three design aspects: structure, function, and behavior. Contributions of this work are to revamp traditional Turing computation paradigm to N-dimension computing machine, yet it is simple, straightforward, and implementable by state-of-the-practice hardware and software technologies. Thus, the burden of solving difficult problems can be lessened.

11 - Computer architectures for the Fifth Generation