Measuring the Performance and Intrinsic Variability of Evolved Circuits

Design of a low-power, high performance, 8×8 bit multiplier using a Shannon-based adder cell

In this paper, we propose novel transmission-gate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All our proposed gates operate in full swing and have less leakage currents, less dynamic power consumption, and shorter delays than conventional CMOS gates. Compared with the conventional 65nm CMOS gates, our proposed 65nm gates can improve leakage currents, dynamic power consumption, and propagation delays by averages of 29.5%, 15.3%, and 30.3%, respectively. Logic synthesizers can use our proposed gates to facilitate power reduction. The experimental results show that Power Compiler can further reduce the leakage current and dynamic power up to 35.0% and 20.0%, respectively, when the standard cell library used by Power Compiler contains our proposed gates.

Compact hardware architectures are proposed for the ISO/IEC 10118-3 standard hash function Whirlpool. In order to reduce the circuit area, the 512-bit function block ρ[k] for the main datapath is divided into smaller sub-blocks with 256-, 128-, or 64-bit buses, and the sub-blocks are used iteratively. Six architectures are designed by combining the three different datapath widths and two data scheduling techniques: interleave and pipeline. The six architectures in conjunction with three different types of S-box were synthesized using a 90-nm CMOS standard cell library, with two optimization options: size and speed. A total of 18 implementations were obtained, and their performances were compared with conventional designs using the same standard cell library. The highest hardware efficiency (defined by throughput per gate) of 372.3 Kbps/gate was achieved by the proposed pipeline architecture with the 256-bit datapath optimized for speed. The interleaved architecture with the 64-bit datapath optimized for size showed the smallest size of 13.6 Kgates, which requires only 46% of the resources of the conventional compact architecture.KeywordsHash functionWhirlpoolHardware architectureCryptographic hardware

Organic thin-film transistors (OTFTs) are drawing increasing attention due to their unique advantages of mechanical flexibility, low-cost fabrication, and biodegradability, enabling diverse applications that were not achievable using traditional inorganic transistors. With a growing number of complex applications being proposed, the need for expediting the design process and ensuring the yield of large-scale designs with organic technology increases. A complete digital standard cell library plays a crucial role in integrating the emerging organic technology into existing computer-aided-design (CAD) flows. In this paper, we present the design, fabrication, and characterization of a standard cell library based on bottom gate, top contact pentacene OTFTs. We also propose a commercial tool compatible, RTL-to-GDS flow along with a new organic process design kit (PDK) developed based on our process. To the best of our knowledge, this is the first open-source organic standard cell library, enabling the community to explore this emerging technology.

Underwater acoustic networks can have large propagation delays as compared to typical packet durations, as a result of the low speed of sound in water. The ill effects of large propagation delay on medium access control (MAC) are well known. Conventional MAC protocol design for such networks focuses on mitigation of the impact of propagation delay. Most proposed protocols to date achieve, at best, a throughput similar to that of the zero propagation delay scenario. We have explored the possibility that propagation delays can be exploited to make throughput far exceed that of networks without propagation delay and shown that the throughput of a N-node wireless network with propagation delay is upper bounded by N/2. In a small set of illustrative network geometries, we can manually determine transmission schedules that allow us to achieve this N/2 bound. However, for a given network, the problem of determining transmission schedules that maximize throughput is as yet unsolved. In this paper, we put forward an algorithm that generates transmission schedules with high throughput for arbitrary network geometries.

This paper presents the design of high speed multiplier and squaring architectures based upon ancient Indian Vedic mathematics sutras. In existing Vedic multiplier architectures, the partial product terms are computed in parallel and then added at the end to get the final result. In this work, all the partial products are adjusted using concatenation operation and are added using single carry save adder instead of two adders at different stages. The high speed Vedic multiplier architecture is then used in the squaring modules. The reduced number of computations in multiplication due to adjusting using concatenation operation and one carry save adder only, the designed multiplier offers significant improvement in speed. The designed architectures are realized using Xilinx Spartan-3E FPGA. The comparison shows the 28.72% and 38.59% reduction in propagation delay for the designed 32-bit multiplier as compared to the existing multiplier designs.

This paper presents a twin precision multiplier with modified 2-D bypass Logic. The multiplier can perform one 8-bit multiplication or two 4-bit multiplications. The multiplier structure is modified by adding a 2-dimensional modified bypassing logic resulting in reduction in dynamic power as well the delay. Simulation results indicate that with a marginal increase in area, the proposed twin precision multiplier achieves an improvement of 25.5% in delay and up to 29% reduction of power-delay product when compared to existing designs.

Error detectors/predictors are inevitable for any power and performance constrained designs. Dynamic voltage and frequency scaling can be efficiently implemented using these error detectors/predictors. In this work, we propose a new area and power efficient error predictor for dynamic voltage and frequency scaling application. In the proposed error predictor, the edge of delayed data of master latch is observed in the high phase of the clock to flag a warning signal. The warning signal determines the point of reduction in the supply voltage without any system failure. Compared to pulse-based error predictor, our timing error predictor consumes 17% less power under 100% switching activity and requires 27% less additional area overhead. The functionality of the proposed FF is tested by implementing ISCAS89 benchmark circuits, 16-bit adder, and 16-bit multiplier. A fully automated insertion flow is adopted to implement the block level designs. Using the proposed FF in a block level implementation shows that it can save power up to 33% in the typical corner compared to conventional worst case design.

This paper presents a comprehensive review of the engineering properties of fly ash concrete in its fresh and hardened form. It is shown that two major factors influence the properties of fly ash concrete—its intrinsic variation in composition, and the philosophy of mix proportioning adopted to produce the concrete. The effects of ash variability can be covered by three basic criteria of mix proportioning—namely, low water-cementitious ratio, inclusion of a water-reducing plasticizer, and an early and long curing period. It is then shown that these criteria can be utilized to produce concrete containing 50% ash replacement and having 40 to 60 MPa 28-day strength, with high workability, low water/cementitious ratios of 0.30 to 0.45, and one-day strengths of 10 to 20 MPa. Properties of strength, elasticity, shrinkage and creep are reported, and durability aspects briefly discussed. The paper unfolds the secret of utilizing the full pozzolanic potential of fly ash in practice.

Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique technique of calculations based on 16 Sutras (Formulae). A high speed complex multiplier design (ASIC) using Vedic Mathematics is presented in this paper. The idea for designing the multiplier and adder/sub-tractor unit is adopted from ancient Indian mathematics “Vedas”. On account of those formulas, the partial products and sums are generated in one step which reduces the carry propagation from LSB to MSB. The implementation of the Vedic mathematics and their application to the complex multiplier ensure substantial reduction of propagation delay in comparison with DA based architecture and parallel adder based implementation which are most commonly used architectures. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using standard 90nm CMOS technology. The propagation delay of the resulting (16, 16)×(16, 16) complex multiplier is only 4ns and consume 6.5 mW power. We achieved almost 25% improvement in speed from earlier reported complex multipliers, e.g. parallel adder and DA based architectures.

State-of-the-art variants of slotted Aloha (S-Aloha) for underwater acoustic networks do not consider the joint effect of retransmission and distance-dependent propagation delay variability, which is one of the most important parameters that affect the performance of any medium access control protocol. In this study, the authors analyse the stability of S-Aloha in a network environment, such as underwater, where propagation delay and its variance are not negligible. A finite number of unbuffered transmitters are considered. Through mathematical analysis, supported by discrete event simulations, they compare the utilisation and stability with S-Aloha in radio frequency environments where propagation delay, as well as delay variance, are negligible. The comparison results indicate that the stability region is appreciably shifted and also there is a significant decrease of utilisation in the presence of retransmission and distance-dependent propagation delay variability.

Quantum-Dot Cellular Automata (QCA) as technology is a promising candidate that has tremendous potential to replace CMOS due to its outstanding features such as low-power, extremely high density, fast operation speed. However, due to its four-phased clocking scheme and timing requirements, various issues in timing for interconnections and feedback are present. In this paper, the delay transfers and retiming using QCA characteristics to solve timing issues has been explored. The problem in assigning appropriate clock zones and feedback has been addressed. Based on the design rules and constraints, retiming technique has been discussed to perform delay-transfer and time-scaling to achieve efficient clock zone assignment. A serial adder has been designed that uses multilayer crossover. As a case study, a 4-bit serial-parallel multiplier has been designed using the serial adder as basic input circuit to illustrate the rules of retiming.

Biological systems are inherently variable, with their dynamics influenced by intrinsic and extrinsic sources. These systems are often only partially characterized, with large uncertainties about specific sources of extrinsic variability and biochemical properties. Moreover, it is not yet well understood how different sources of variability combine and affect biological systems in concert. To successfully design biomedical therapies or synthetic circuits with robust performance, it is crucial to account for uncertainty and effects of variability. Here we introduce an efficient modeling and simulation framework to study systems that are simultaneously subject to multiple sources of variability, and apply it to make design decisions on small genetic networks that play a role of basic design elements of synthetic circuits. Specifically, the framework was used to explore the effect of transcriptional and post-transcriptional autoregulation on fluctuations in protein expression in simple genetic networks. We found that autoregulation could either suppress or increase the output variability, depending on specific noise sources and network parameters. We showed that transcriptional autoregulation was more successful than post-transcriptional in suppressing variability across a wide range of intrinsic and extrinsic magnitudes and sources. We derived the following design principles to guide the design of circuits that best suppress variability: (i) high protein cooperativity and low miRNA cooperativity, (ii) imperfect complementarity between miRNA and mRNA was preferred to perfect complementarity, and (iii) correlated expression of mRNA and miRNA – for example, on the same transcript – was best for suppression of protein variability. Results further showed that correlations in kinetic parameters between cells affected the ability to suppress variability, and that variability in transient states did not necessarily follow the same principles as variability in the steady state. Our model and findings provide a general framework to guide design principles in synthetic biology.

Multiplication represents one of the major bottlenecks in most digital processing systems. Depending on the wordsize, several partial products are added to evaluate the product. The well-known shift-and-add algorithm uses minimal hardware but has unacceptable performance for most applications. Several parallel fast multiplication schemes have been suggested using several levels of blocks containing full adders. This paper presents the design of a fast multiplier implemented using either (7,3) parallel counter or (7:3) compressor circuits for implementation in CMOS technology, The resulting 16 by 16-bit multiplier has less delay than conventional fast multipliers, although the gate count is about 10% higher.

Design, analysis and test of conventional and winglet propellers under highly loaded conditions