Memory Organization and Structures for On-Chip Learning in Spiking Neural Networks

Spiking neural network (SNN) has drawn research interests as it mimics dynamic activities of human brain and has the potential to perform real-time cognitive tasks. However, latency, throughput and flexibility of existing hardware implemented SNNs are limited. The conventional rate coding is inefficient in terms of accuracy and latency. Oversimplified SNN models adopted by neuromorphic hardware discard characteristics such as neuron dynamics and filter effects etc., which are critical for neural information processing. Recent research advancements show that the potential of SNN can be better utilized by moving beyond rate-based model and considering temporal information embedded in the spike sequences. However, these works employ complex biologically realistic SNN models, posing challenges to hardware complexity. Furthermore, most existing neuromorphic hardware are developed for specific SNN models, or aiming at replicating biological behaviors. There is a lack of general methodology for SNN design optimization. Novel hardware architecture and systematic optimization techniques are required for efficient FPGA implementation and support flexible SNN models. To address above issues, in this work we proposed a holistic optimization framework for encoder, model, and architecture design of FPGA based neuromorphic hardware. We present an efficient neural coding scheme and training algorithm, which can optimize encoder parameters to enable fast inference. A flexible and hardware-friendly model is proposed, in which SNNs are represented as a network of Infinite Impulse Response (IIR) filters. Finally, an end-to-end framework is developed to optimize and deploy FPGA implementation. Experimental results show our work achieves state-of-the-art accuracy in various classification tasks, and outperforms various platforms including CPU, GPU and dedicated neuromorphic processors in terms of latency and throughput.

Comparison of spiking neural networks with different topologies based on anti-disturbance ability under external noise

Spiking Neural Network (SNN) is the most recent computational model that can emulate the behaviors of biological neuron system. This paper highlights and discusses an efficient hardware architecture for the hardware SNNs, which includes a layer-level tile architecture (LTA) for the neurons and synapses, and a novel routing architecture (NRA) for the interconnections between the neuron nodes. In addition, a visualization performance monitoring platform is designed, which is used as functional verification and performance monitoring for the SNN hardware system. Experimental results demonstrate that the proposed architecture is feasible and capable of scaling to large hardware multilayer SNNs.

Neuromorphic computing is a promising technology for future machine learning research, which is envisioned to provide lower power consumption, fault tolerance, and massive parallelism. However, the neuromorphic network, i.e., spike neural network (SNN), suffers from a broader range of its application compared with artificial neural networks (ANN). In this work, we propose a stochastic computation SC-based hybrid ANN and SNN scheme, which supports both ANN and SNN computation in SC domain. The ANN computation is converted to SC, which is implemented with simple logic gates. Moreover, we propose a new two-stage stochastic computation that is compatible with the sequence computation style of SNN. Consequently, the logic resource for the hybrid SNN and ANN can be shared. Compared to the state-of-the-art hybrid scheme, the proposed SC-based ANN and SNN exhibit much lower hardware costs and higher hardware efficiency.

Conventional hardware platforms are far from reaching real-time simulation requirements of complex spiking neural networks (SNN). Therefore we designed an accelerator board with a neuro-processor-chip, called NeuroPipe-Chip. In this paper, we introduce two new concepts on chip-level to speed up the simulation of SNN. The concepts are implemented in the architecture of the NeuroPipe-Chip. We present the hardware structure of the NeuroPipe-Chip, which is modelled on register-transfer-level (RTL) using the hardware description language VHDL. We evaluate the performance of the NeuroPipe-Chip in a system simulation, where the rest of the accelerator board is modelled in behavioral VHDL. For a simple SNN for image segmentation, the NeuroPipe-Chip operating at 100 MHz shows an improvement of more than two orders of magnitude compared to an Alpha 500 MHz workstation and approaches real-time requirements for SNN in the order of 10/sup 6/ neurons. Hence, such an accelerator would allow real-time simulations of complex SNN for image processing. Currently, the implementation of the NeuroPipe-Chip in a 0.35 m digital CMOS technology is investigated.

Neuromorphic computing has emerged as a highly promising paradigm for energy-efficient and real-time processing of event-driven workloads such as spiking neural networks (SNNs). These systems mimic the sparse and asynchronous communication behavior of the brain, and are particularly well-suited for edge AI, robotics, and low-power sensory processing. However, as neuromorphic processors scale to support larger and more complex SNNs, the communication infrastructure becomes a primary bottleneck. Conventional Network-on-Chip (NoC) architectures--while widely used in many-core systems--are ill-suited for neuromorphic workloads due to their reliance on area and energy intensive buffers, routing tables, and continuous link activity. Moreover, NoCs often fail to accommodate the bursty, multicast, and temporally sensitive nature of SNN traffic, leading to spike loss, latency variation, and unnecessary power dissipation. This dissertation introduces a comprehensive interconnect solution based on the segmented ladder bus, a lightweight and scalable bus architecture optimized for spiking communication. The first contribution is the design of ADIONA, a dynamic segmented ladder bus architecture that leverages bufferless switching and compile-time programmability to enable multiple concurrent paths with low energy and latency. ADIONA's segmented topology and runtime control provide flexibility while maintaining deterministic behavior and hardware simplicity. To support application-level deployment on ADIONA, the second major contribution is MASS--a mapping and scheduling framework for SNNs on segmented buses. MASS includes: (1) a heuristic-based cluster mapping strategy to minimize spike loss and communication energy, (2) a traffic scheduling algorithm to prevent path collisions through temporal grouping, and (3) a path routing method that minimizes path length and congestion. Experimental results show that MASS eliminates spike loss and reduces interconnect energy by up to 13.5% compared to randomized baselines, while supporting high-throughput traffic patterns. The final contribution is an efficient architecture proposal and a hardware realization of the control plane, via a scenario-aware controller implemented on FPGA. To manage control plane scaling complexity, we propose two algorithms--greedy grouping and maximal clique extraction--to compress switch control scenarios and minimize memory usage. Our FPGA results show that the control plane occupies less than 10% of the total area and scales sublinearly with the network size, validating the practicality of the approach. Together, these contributions form a complete and scalable communication framework for neuromorphic systems, spanning architectural design, algorithmic optimization, and hardware implementation. The segmented ladder bus offers a promising path toward future neuromorphic processors that demand low-power, low-latency, and scalable interconnects.

Deep Neural Networks (DNNs) have been successfully applied to various real-world machine learning applications. However, performing large DNN inference tasks in real-time remains a challenge due to its substantial computational costs. Recently, Spiking Neural Networks (SNNs) have emerged as an alternative way of processing DNN'fs task. Due to its eventbased, data-driven computation, SNN reduces both inference latency and complexity. With efficient conversion methods from traditional DNN, SNN exhibits similar accuracy, while leveraging many state-of-the-art network models and training methods. In this work, an efficient neuromorphic hardware architecture for image recognition task is presented. To preserve accuracy, the analog-to-spiking conversion algorithm is adopted. The system aims to minimize hardware area cost and power consumption, enabling neuromorphic hardware processing in edge devices. Simulation results have shown that, with the MNIST digit recognition task, the system has achieved $\times 20$ reduction in terms of core area cost compared to the state-of-the-art works, with an accuracy of 94.4%, core area of 15 $\mu m^{2}$ at a maximum frequency of 250 MHz.

Case-based reasoning (CBR) methodology stems from research on building computational memories capable of analogical reasoning, and require for that purpose specific composition and organization. This main task in CBR has triggered very significant research work and findings, which are summarized and analyzed in this article. In particular, since memory structures and organization rely on declarative knowledge and knowledge representation paradigms, a strong link is set forth in this article between CBR and data mining for the purpose of mining for memory structures and organization. Indeed the richness of data mining methods and algorithms applied to CBR memory building, as presented in this chapter, mirrors the importance of learning memory components and organization mechanisms such as indexing. The article proceeds through an analysis of this link between data mining and CBR, then through an historical perspective referring to the theory of the dynamic memory, and finally develops the two main types of learning related to CBR memories, namely mining for memory structures and mining for memory organization.

As deep learning models scale, they become increasingly competitive from domains spanning from computer vision to natural language processing; however, this happens at the expense of efficiency since they require increasingly more memory and computing power. The power efficiency of the biological brain outperforms any large-scale deep learning (DL) model; thus, neuromorphic computing tries to mimic the brain operations, such as spike-based information processing, to improve the efficiency of DL models. Despite the benefits of the brain, such as efficient information transmission, dense neuronal interconnects, and the co-location of computation and memory, the available biological substrate has severely constrained the evolution of biological brains. Electronic hardware does not have the same constraints; therefore, while modeling spiking neural networks (SNNs) might uncover one piece of the puzzle, the design of efficient hardware backends for SNNs needs further investigation, potentially taking inspiration from the available work done on the artificial neural networks (ANNs) side. As such, when is it wise to look at the brain while designing new hardware, and when should it be ignored? To answer this question, we quantitatively compare the digital hardware acceleration techniques and platforms of ANNs and SNNs. As a result, we provide the following insights: (i) ANNs currently process static data more efficiently, (ii) applications targeting data produced by neuromorphic sensors, such as event-based cameras and silicon cochleas, need more investigation since the behavior of these sensors might naturally fit the SNN paradigm, and (iii) hybrid approaches combining SNNs and ANNs might lead to the best solutions and should be investigated further at the hardware level, accounting for both efficiency and loss optimization.

This chapter discusses advantages and features of Spiking Neural Network (SNN) hardware, which serve as the motivation. It presents the hardware‐friendly learning algorithm is implemented in hardware. An event‐driven computation has the potential to be energy‐efficient as spikes in the network are often sparse. At the same time, however, it demands specialized hardware that can match this event‐triggered computational model. The feature of inferring with a progressive precision provides one extra freedom in optimizing the system performance. Many large‐scale neuromorphic engines based on digital SNNs have been developed to help understand how the brain works and also to provide an efficient way of computing. The chapter reviews a few examples of large‐scale SNNs in digital form. The chapter shows how the learning algorithm can be applied to a memristor‐based neural network. It introduces algorithms and hardware architectures to serve as a case study for implementing analog/mixed‐signal SNNs with a crossbar structure.

Spike-timing dependent plasticity (STDP)-based spiking neural network (SNN) is a promising choice to realize unsupervised intelligent systems with a limited power budget. In addition to STDP, another two bio-inspired mechanisms of lateral inhibition and homeostasis are always implemented in the unsupervised training procedure of STDP-based SNNs. However, the existing methods to achieve lateral inhibition necessitate a great number of connections that are proportional to the square of the number of learning neurons, and the existing hardware solution of homeostasis demands complex circuits for each learning neuron, both of which challenge the hardware implementation of STDP-based SNNs. In this brief, we propose a novel SNN using memristor-based inhibitory synapses to realize the mechanisms of lateral inhibition and homeostasis with low hardware complexity. The proposed SNN can improve the network scalability by reducing the connection number for lateral inhibition from $N^{2}$ to $N$ and reduce the hardware overhead by leveraging the circuit of lateral inhibition to achieve homeostasis. Software simulations on the recognition task on MNIST dataset show that the proposed SNN achieves a ~ 2 times higher learning efficiency with comparable accuracy. In addition, the challenging properties of realistic memristor devices, including limited number of resistive states, intrinsic parameter variation, and permanent open device, are added in the simulation to evaluate the robustness of our proposed approach.

Organizational knowledge is vital to the realization of goals of organizations. Effective use of this knowledge depends on the selective use of organizational memory. The term organizational memory is concerned with how organizations collect, store, and provide access to experience, skills and know-how. Schools are special organizations in the sense that they promote learning. Its organizational knowledge decides its competitive capacities, while its organizational memory decides its ability to develop persistently. In order to facilitate school organizational learning and memory, we present, by analogy of the mechanism of human memory, a model of school organizational memory process basing on relevant theories and researches of knowledge management. This model incorporates multiple phases of personal and social knowledge conversion that can be compatibly supported by virtual learning environments. This paper also introduces our practice with a virtual learning environment called PRIME, designed specially to support this model. We hope that our research can provide a theoretical framework for school knowledge creation and accumulation, and attract more attention to school knowledge organizational knowledge and memory.

Spiking neural network (SNN) hardware relies on implicit assumptions that prioritize dendritic/synaptic learning above axon/synaptic concerns, compromising performances in signal capacity, accuracy, and compactness of SNN systems. Herein, we develop an artificial axon by utilizing the heterogeneity and interface state tunability in anisotropic two-dimensional (2D) tellurium (Te). By operating a multiterminal axon under the bioelectricity level, the device achieved neuron-like heterogeneous axon dynamics expansion (∼258%). An excellent dendritic-like tunability (∼197%) exhibits gain on the axons. The synergistic axon-dendrite optimization device exhibits 5-bit programmable conductance, signal filtering, and input enhancing. The accuracy of recognizing data sets based on the SNN algorithm demonstrates efficient optimization (5.2% higher accuracy) of networks by the device features, especially in the case of performing image preprocessing. This artificial neuron solution with anisotropic 2D materials utilizing biomimetic interface engineering provides a universal strategy for compact, high-precision parallel architecture of SNN hardware.

Neuro-evolutionary algorithms optimize the synaptic connectivity of sets of candidate neural networks based on a task-dependent fitness function. Compared to the commonly used methods from machine learning, many of them not only support the adaptation of connection weights but also of the network topology. However, the evaluation of the current fitness requires running every candidate network in every generation. This becomes a major impediment especially when using biologically inspired spiking neural networks which require considerable amounts of simulation time even on powerful computers. In this paper, we address this issue by offloading the network simulation to SpiNNaker, a state-of-the art neuromorphic hardware architecture which is capable of simulating large spiking neural networks in biological real-time. We were able to apply SpiNNaker's simulation power to the popular NEAT algorithm by running all candidate networks in parallel and successfully evolved spiking neural networks for solving the XOR problem and for playing the Pac-Man arcade game

Developing energy-saving neural network models is a topic of rapidly increasing interest in the artificial intelligence community. Spiking neural networks (SNNs) are biologically inspired models that strive to leverage the energy efficiency stemming from a long process of evolution under limited resources. In this paper we propose a SNN model where each neuron integrates piecewise linear postsynaptic potentials caused by input spikes and a positive bias, and spikes maximally once. Transformation of such a network into the ANN domain yields an approximation of a standard ReLU network, leading to a facilitated training based on backpropagation and an adaptation of the batch normalization. With backpropagation-trained weights, SNN inference offers a sparse-signal and low-latency classification, which can be readily adapted for a stream of input patterns, lending itself to an efficient hardware implementation. The supervised classification of MNIST and Fashion-MNIST datasets, using this approach, provides accuracy close to that of an ANN and surpassing other single-spike SNNs.