Memory reduction through higher level language hardware

We execute the quantum eraser, the Elitzur–Vaidman bomb, and the Hardy’s paradox experiment using high-level programming language on a generic, gate-based superconducting quantum processor made publicly available by IBM. The quantum circuits for these experiments use a mixture of one-qubit and multi-qubit gates and require high entanglement gate accuracy. The results aligned with theoretical predictions of quantum mechanics to high confidence on circuits using up to 3 qubits. The power of quantum computers and high-level language as a platform for experimenting and studying quantum phenomena is henceforth demonstrated.

The level of support for high level programming languages (HLPLs), despite the claim of support by some of the newly introduced microprocessors, is inadequate despite the falling (rising) cost of hardware (software). Computer systems that are to be used to run programs written exclusively in HLPLs have a need for a multiprocessor/multiarchitecture microprocessor design (M3D); the personal/desk-top computers are prime examples. The HLPLs that will be used in programming these systems will be grouped according to their structures. Each group of languages will require their own instruction set; the hardware and software needs will determine the type of architecture configuration, i.e. aspects such as: register-to-register, memory-to-memory, stack, or a combination of these. The overall system should be divided up into functional units, e.g. ALU, compiler/translator, etc. Each functional or subfunctional unit will be implemented in software, firmware, hardware, or a combination of these with implementation decision based on the speed criticality, cost, technology, and the need to modify the unit. This approach will lead to a cop-down-design, and will also reduce the semantic gap, software and system cost, and down-time.

A characterization of very high level language is given that distinguishes them from merely high level languages. Three languages, APL, SETL, and BDL, are examined to justify this characterization.

Most simulations of communications systems are done using a high-level language such as Matlab or C. As the complexity of these simulations grows and higher performance is expected, the runtime of the simulations becomes unacceptable. A promising solution to this problem is to move frequently executed (bottleneck) sections of the simulation into dedicated hardware that is implemented on field-programmable gate arrays (FPGAs). An FPGA, coupled with a very high-speed interface to the PC, is an ideal platform for such an accelerator. The system described in this paper is based on a PCI board with multiple Xilinx FPGAs. A typical wireless communications channel can be described as a finite impulse response (FIR) filter with time-varying coefficients. In this paper a FIR filter is implemented using dedicated hardware mapped onto a Xilinx FPGA board. The filter has additional hardware that interpolates between adjacent coefficients for more continuous and realistic results. The same filter is created in optimized Matlab for software simulation. Another common algorithm implemented in modern communication systems is a fast Fourier transform (FFT). This paper compares the software simulation and co-simulation approaches for both the FIR and the FFT blocks. Dramatic improvements in overall simulation throughput are demonstrated by using the hardware accelerator, as opposed to a pure software simulation

Only recently has the design of computer architectures deviated from the Von Neumann style. Most architectures based on the Von Neumann architecture suffer from what is called 'the semantic gap'. This means that the objects and operations in a high level language (HLL) are not closely related to the objects and operations in the architectures that execute the HLL [1]. This paper addresses the issues involved in the semantic gap problem, by formulating a framework based on 'information structures' that would aid in the design of HLL architectures. First digital computers are defined based on 'information structures'. Execution of a program in an HLL is defined in terms of transformations on information structures. An architecture design methodology is proposed and some comments about performance are made. Finally different ways of implementing information structures are considered.

Last 14 months students and teachers faced a necessity to realize students’ self-control at the temporary or permanent absence of help from the teachers’ side at degradation of teaching quality from teachers’ side and decreasing of perception quality from the students’ side in online mode of studying process. Such self-control will help to student to check him/herself independently, will increase the self-evaluation and self-confidence and will improve the quality and depth of knowledge. Students of the different educational institutions study at least one high level programming language, automation of calculations in electronic spreadsheets. Also students of different technical specialties study mathematical application software. Some students also study even more specific software for industry automation development. Therefore it’s proposed to realize the following ways for students’ self-checking at different technical tasks solving. 1. High level programming language. 2. Electronic spreadsheets. 3. Mathematical application software. 4. Application software for industrial automation systems development. Obtained results must be compared by student and solutions must be reanalyzed independently at the results mismatch.This self-checking approach is partly realized for students of technical specialties who study academic subjects like “Information technology”, “Computer technology”, “Programming of PLCs”. Exactly the last one requires the corresponding knowledge obtained during another academic subject learning.Proposed approach allows the refreshing of earlier obtained knowledge, the obtaining of new knowledge at new application software studying, to realize self-control at performance of different technical tasks at different subfields of information technologies studying and to increase the self-evaluation and self-confidence as a result.KeywordsSelf-controlOnline educationAutomation systems and data transfer networksPLC programmingMaritime branch

The SYMBOL 2R Computing System represents an attempt to bridge the gap between machine languages and higher level programming languages. This gap has always limited the users' ability to communicate with the machine, thus creating a communication problem. Early attempts at solving this communication problem consisted of developing a series of user-oriented programming languages, i.e., assembler languages and higher level languages, supplemented with a host of translator programs that would transform the higher level languages into machine language. For several years it seemed that this approach represented the only economically feasible solution. In 1965, W. H. Burkhardt (2) suggested the development of high-level language computers Burkhardt did suggest that the availability of low cost components would make high-level language computers an economically feasible solution. In fact, the recent decline in the cost of components as compared with the steady, if not increasing cost of the software needed to develop and maintain compilers for high-level languages, has made the high-level language computer solution seem even more attractive.

The ULowell Data Flow Project combines dataflow hardware, dataflow software, and a data flow development environment. The hardware component, a data flow coprocessor card, utilizes seven NEC 7281 Image Pipelined Processors. Each chip models a static dataflow computation and is programmable. The coprocessor was designed and implemented by ULowell personnel and uses an AMIGA 2000 as a host. The software component currently consists of a library of data flow image processing algorithms and an evolving software development environment. Currently the image processing library includes typical imaging operations such as: edge enhancement, filtering, histogramming, and affine transformation. The software development environment (SDE) is depicted in Figure 1. The SDE contains a Data Flow Graph Editor which programmers use to design their data flow code. The data flow algorithm can then be converted directly into NEC data flow assembly code which is then assembled using the ULowell Data Flow Assembler. The assembler differs from NEC's assembler in that it can produce relocatable code. The object code output of the assembler is given to the Data Flow Resource Manager. The resource manager monitors the available resources within the chips. Thus, if a single process does not totally utilize a chip's table space or memory, then a second process may be concurrently loaded onto the same chip. The ability to have multiple data flow processes coexisting within a single chip is unique to the ULowell environment. The data flow resource manager can download and monitor code to either the hardware or to a software simulator/debugger. The simulator/debugger can monitor and trace data flow tokens as they proceed through the chip. Output of the simulator/debugger can be fed back into the data flow graph editior to visually trace token flow through the original program design. The last component of our SDE is a High Level Language translator which can compile programs written in SISAL, a high level language for parallel computation, down to NEC 7281 assembly language. We have already implemented the relocatable assembler, and the data flow resource manager. Prototype versions of the high level translator, simulator/debugger and graph/editor are currently being implemented.

PROMELA is a high level modeling language for model checking purpose. PROMELA model can be checked using SPIN (Simple PROMELA Interpreter) model checker to ensure formally some specifications hold in the model. However, PROMELA does not have formal and clear semantics. It is interpreted under SPIN implementation only and thus is bounded into SPIN. With high-level language it has, PROMELA has gain fame in model checker world due to its easiness to capture process model using high level language. Describing PROMELA formal semantic is a good way to broaden PROMELA usage. One of PROMELA feature is the ability to model concurrent processes, in which the concurrent process may not start from the same time point. This feature, called dynamic process creation, is essential to be noticed, to ensure that state-transition of PROMELA model is correct. Dynamic process creation in PROMELA should be defined formally, we use Labeled Transition Systems (LTSs) to describe formal semantic of PROMELA dynamic process creation.

The goal of this paper is to analyse semantics of algorithms with explicit continuous time with further aim to find approaches to automatize model checking in high level, easily understandable languages. We give here a general notion of timed transition system and its formula representation that are sufficient to deal with some known examples of timed algorithms. We prove that the general semantics gives the same executions as direct, more intuitive interpretations of executions of algorithms. In a way, we try to give a general treatment of considerations of Yu.Gurevich and his co-authors concerning concrete Gurevich machines (called evolving algebras in [Gur95]), in particular, related to Railroad Crossing Problem [GH96]. Besides that we formalize specifications of this problem in a high level language which permits to rewrite directly natural language formulations, and to give a formal proof of correctness of the railroad crossing algorithm using rather a small amount of logical means, and this leads to hypotheses how automatize inference search.

Nowadays, the growth of the educational sector generates massive data such as details of students, staff and their academic performance, administrative and research details, etc. These data are stored in distributed databases. The parallel database performs parallel query processing hence, the query processing time is reduced and throughput for the transaction processing is improved. The parallel database system also improves the performance by employing parallelism through various database management operations such as loading the data, building indexes, and evaluating queries. The data is partitioned and placed across multiple disks for parallel input and output (I/O) operation to achieve parallelism on queries using pipeline parallelism. The individual relational operations such as sort, join, aggregation, etc. are executed in parallel database by each processor that works independently with its own partition. Queries are expressed in high level language such as structured query language (SQL) that are translated into relational algebra for query processing. Thus, the parallel database increases the throughput in database management and reduces the query processing time. This paper presents a parallel database for student counselling for engineering university admission using MySQL relational database management system.

Correctness checking of HDL-model behavior is an integral part of runtime verification of hardware. As a rule, it is based on comparing of HDL-model behavior and reference model behavior, developed in high-level programming languages. Being verified, both models are stimulated with the same input sequence; their output traces are caught and matched. Due to the abstractness of the reference model, the matching is not a trivial task as event sequences can be different and some events of one trace may miss in the other one. A methodology of runtime trace matching for hardware models of different abstraction levels is suggested in this paper. The methodology has been successfully applied to a number of industrial projects of unit-level microprocessor verification.

By analyzing the measuring principle of tool maker's microscope, the article presents a new method for thread measurement with a tool maker's microscope assisted by computer. Special real-time image sampler was developed. A new measuring system was established and relative software has been designed. For the hardware design, the technique of DMA transfer data was adopted and the real-time sampling of one field of image was realized. For the software design, both assembly language and high level language were used. Image sampling and edge detection were operated by assembly language rapidly and the thread parameters were calculated by high level language. Experiments show that the system can measure the thread parameters automatically and rapidly. The study of computer-aided measurement of thread accuracy with a tool maker's microscope is useful to realize the intelligent measurement of another shape accuracy with a tool maker's microscope.

S1: Status of Hardware and Software for Microcomputers

RISC