Memristor-based Reconfigurable True Time Delay Circuit

The design, analysis, and implementation of an accurate delay circuit used to synthesize critical paths in a microprocessor system are presented. The delay circuit includes a novel 64-step programmable calibration delay line that is highly uniform across a wide range of supply voltages and a reconfigurable delay path with tunable delay sensitivity to voltage variations. The calibration delay line generates delay step in picosecond range, which is less than 1% of the clock cycle time for the microprocessor. The reconfigurable path is capable of increasing voltage sensitivity of the delay circuit by 40% and emulating the steeper frequency versus voltage slope of the microprocessor in low-voltage domain. The proposed circuit is implemented inside the critical path monitor block placed on a test microprocessor core fabricated using 22-nm silicon-on-insulator CMOS process. Measurement results from nine test cores show that the circuit tracks microprocessor timing margin change with an error less than 1.3% of the core operating frequency over a wide supply voltage range.

A novel reconfigurable negative group delay (NGD) circuit based on branch-line coupler is proposed in this article. It consists of two branch-line couplers that are connected by two varactors with different capacitance values. By simply adjusting the capacitance values, both the transmission gain/loss and group delay (GD) values of the proposed circuit can be independently adjusted as desired. Full theoretical analysis has been given to verify the reconfigurable NGD responses. To compensate for the transmission loss, an active NGD circuit is also proposed by inserting two simple amplifiers in the transmission paths. The active circuit can also achieve independent transmission gain/loss and GD by tuning the amplifiers’ gain with fixed capacitance value. Passive and active prototypes were designed, fabricated, and tested to demonstrate the proposed techniques. The experimental results show that NGD of the proposed passive circuit can be adjusted from 0 to −90 ns, while the gain varies from −14 to −53 dB. The GD of active circuit can also be adjusted from 0 to −80 ns, while the gain varies from 17 to −18 dB. These experimental results agree well with simulations.

A novel tunable non-Foster T-network loaded with transmission lines (TLs) using a two-stage distributed amplifier (DA)-based negative group delay (NGD) circuit is proposed. The tunability comes from the NGD response synthesized by adjusting the ratio of the transconductance of the transistors, and the varactors at both the input and output port. Due to the distributed topology, the proposed T-network not only works within a relatively broad band (several hundreds of Mega-Hertz), but also has good input and output matching characteristics. A prototype of the proposed non-Forster T-network is built and tested. By properly amending the in-band magnitude and phase characteristics, the NGD circuit can realize the targeted non-Foster T-network with unconditional stability. The experimental results show that the tunable equivalent T-network has a 0 pF to − 1.5 pF shunt capacitance and a 0 nH to −1.875 nH inductance.

We present a new model for dynamic reconfiguration costs. The model targets both, reconfiguration time and data. Reconfiguration is modeled at the granularity of reconfigurable resources, hence the model can take advantage of the partially identical configurations. We apply the model to binary configuration data to generate cost efficient bitstreams for reconfigurable systems. It is shown how the model relates to previously established reconfiguration techniques. The improvements in reconfiguration time and bitstream size are demonstrated on an example. The model also provides a measure for the similarity of reconfigurable circuits. We present the application of the reconfiguration model for high level designs. The model describes in detail, which circuit elements are static and which need to be reconfigured. We use the model as a cost function in a high level synthesis tool to derive an allocation with minimal reconfiguration costs.

A high electromagnetic pulse protection method based on time delay circuit has been presented. The slow wave structures are cleverly used to implement super early response, which can protect the sensitive equipment from the high electromagnetic energy. Firstly, the protection method based on the principle of time delay circuit is introduced. Then the feasibility is verified by ADS simulation software. A protection module is realized and tested at last. The measured results show that the insertion loss is less than 3dB at the frequency band 30MHz to 300MHz, the response time is 5 ns, and the blocking effects for both continuous wave signal and pulse signal are very good. This proposed method would be fit for widely application in RF front-end protection.

A novel circuit scheme is presented for the design of reconfigurable negative group delay circuit (RNGDC) with very low signal attenuation (SA), which is based on a lossy coupled‐line Microstrip (MS) resonator. Theoretical analysis indicates that reconfigurable characteristics in the proposed circuits can be obtained by tuning the resistance of the variable resistor, which is loaded at a specific point on the MS resonator. Based on the study of one‐stage RNGDC, a two‐stage RNGDC arranged in an anti‐symmetrical manner is designed to provide an extended reconfigurable negative group delay range. To validate the performance of the proposed circuit scheme, the prototypes of one‐stage and two‐stage RNGDC have been designed working at a center frequency of 1.73 GHz. Measured results of the two‐stage RNGDC exhibit a group delays variation of −2 ns to −10 ns with signal attenuation variation of −4.5 dB to −9.3 dB at the center frequency, which demonstrates much lower SA compared to the previously‐reported RNGDCs.

Field programmable gate arrays (FPGAs) are considered as a good platform for digital evolvable hardware systems. Researchers introduced virtual reconfigurable circuits as the response to the insufficient support of partial reconfiguration in early FPGAs. Later, the features of FPGAs allowed the designers to develop evolvable systems fully exploiting native reconfiguration infrastructures. Xilinx recently introduced a new platform called Zynq-7000 all programmable (AP) system-on-chip (SoC) which has the potential to become the next revolutionary step in evolvable hardware design. The paper analyzes Zynq-7000 AP SoC from the perspective of an evolvable hardware designer. Several scenarios are described of how to implement evolvable systems on a developmental board equipped with this programmable SoC. These scenarios are evaluated in terms of area overhead, execution time, reconfiguration time and throughput. The resulting observations should be useful for those who are going to develop real-world evolvable systems on the Zynq-7000 AP SoC platform.

In this paper we present the design, realization, and experimental characterization of a photonic integrated true time delay circuit on a CMOS-compatible Si3N4 platform. The true time delay circuit consists of an optical side band filter for single side band modulation and an optical ring resonator for broadband time delay. Two methods of optical delay tuning are investigated: 1) optical wavelength and 2) thermo-optic delay tuning. The wavelength controlled tuning enables a large delay tuning range and can be done remotely from a distant location. The close to a linear phase measurements can be used for full beam-scanning of radio signals with frequencies in the 20 GHz band. The thermal control results in a 5 GHz RF delay bandwidth. A proof-of-concept 2 × 1 beamforming is demonstrated in the 20 GHz band. The design presented here can be employed to realize multi-beams for multi-users serviced by multiple satellites.

We present the design and development of an amplitude compensated long time delay circuit (LTD) in multilayer liquid crystal polymer (LCP) films. The design is implemented with MEMS switches. An LTD is built on a thin-film multilayer stack to provide a variety of transmission lines to offer different attenuation characteristics for amplitude compensation. True time delay (TTD) components produce 0 ps, 200 ps, 400 ps, and 600 ps relative delays. This part is intended to work over wide frequency ranges from DC to 10 GHz. Insertion loss mismatch between delays is measured to be less than ±0.4 dB across the band.

We design, fabricate, and characterize a 7-bit reconfigurable optical true time delay line consisting of Mach-Zehnder interferometer (MZI) switches on the silicon photonics platform. Variable optical attenuators (VOAs) are embedded to suppress the inter-symbol crosstalk caused by the finite extinction ratio of switches. The device can provide a maximum of 1.27 ns delay with a 10 ps resolution over a wide wavelength range. Eye diagram measurement of a 25 Gbps 2(51)-1 pseudo-random bit sequence (PRBS) signal reveals the power penalties only increase 0.17 dB and 0.77 dB after transmission through the shortest (reference) and the longest (1.27 ns delay) paths, respectively.

A scalable and reconfigurable optical true time delay line consisting of high performance MZI switch driving by a parallel graphene heater easily scaled to M bit with a slight increase in dimensions was proposed.

In this study, a four-element prototype of the microwave sampling beamformer structure is constructed and tested. The prototype is composed of the microwave hardware and control hardware. A new compact switch is designed and utilized in the structure. The control circuitry is a four-branch time delay and pulsewidth control circuits along with p-i-n diode drivers. The beamforming structure is designed to have 8-bit phase shifter resolution and 12-bit attenuation resolution. For each antenna element the phase shift and attenuation are controlled through the time delay and pulsewidth of the corresponding pulse train. Different beamforming examples such as beam steering, sidelobe level (SLL) control and null forming are examined with the prototype. It is observed that the structure scans the beams to the proper steering angles. SLL close to -30 dB and nulls deeper than -30 dB are measured.

For the two colour (3∼5um and 8∼12um) sensor fusion, an optical method can replace the electric time delay and integration (TDI) circuit. During the fusion process, there exits an optimal relative gain setting between the two preamplifiers of the sensors. The optical method can provide a real time (30 frames) single enhanced dual band thermal image with an improved signal to noise ratio and better system performance.

A reconfigurable dead-time circuit intended for optimum power-converters' operation is presented. The circuit provides a programmable delay element to produce a wide range of dead-time delays for different power conversion's applications with various loads and input voltages. The circuit utilises two tunable Schmitt triggers, two reconfigurable capacitive banks, and two adjustable-current sources. The post-layout simulation results show that the circuit can produce a wide range of dead-time delays, from 12.8 ns to 952.24 ns, between the control signals of the high and low sides of a power converter. The power consumption of the presented circuit ranges between 323.1 and 89.69 μW, pendant on the selected delay. The presented circuit is implemented in a 0.35-μm AMS CMOS technology where occupies an area of 150 μm×260 μm.

Field programmable gate array (FPGA) devices, heavily used in spacecraft electronics, have grown substantially in size over the past few years, causing designers to work at a higher conceptual level, with computer aided engineering (CAE) tools synthesizing and optimizing the logic from a description. It is shown that the use of commercial-off-the-shelf (COTS) CAE tools can produce unreliable circuit designs when the device is used in a radiation environment and a flip-flop is upset. At a lower level, software can be used to improve the SEU performance of a flip-flop, exploiting the configurable nature of FPGA technology and on-chip delay, parasitic resistive, and capacitive circuit elements.