Methodology for 3-dimensional high-density capacitor reliability evaluation

This paper presents a comprehensive study of the impact of Hot Carrier Injection (HCI) on differential LC Voltage Controlled Oscillator (VCO) reliability tests. Although Negative Bias Temperature Instability (NBTI) has been recognized as major cause for reliability degradation of advanced circuits, HCI-induced degradation may become significant due to the accelerated aging of reliability tests leading to incorrect circuit lifetime prediction. To distinguish HCI effects, different stress voltages and frequencies are applied in Constant Voltage Stress (CVS) and Ramp Voltage Stress (RVS) tests. It is verified that the stress voltage and frequency dependence of time and voltage exponents in the reliability tests are due to the effect of HCI. Based on the observed results, a methodology is proposed to define proper stress conditions for accelerated circuit reliability tests for better lifetime prediction.

This paper presents an experimental work investigating the failure data of oil-impregnated paper under pulsating DC voltage. The failure data of the oil-impregnated paper specimens were obtained through constant voltage stress tests; the Weibull distribution was used to estimate the statistical distribution of failure data. The exponential function (EF) and the inverse power function (IPF) were used to modify the Weibull distribution of failure data, so as to obtain two dual-variable Weibull failure distributions (WFDs), which were used to analyze failure data of oil-paper specimens obtained under pulsating DC and individual DC and AC voltages. Their adequacies were evaluated by using failure data obtained through the constant stress tests under various voltages. Both EF-modified and IPF-modified WFDs show more adequacy for failure data of oil-paper insulation under DC and pulsating DC voltages than AC voltages. The EF-modified WFD was more adequate than IPF-modified WFD in estimating the statistical distribution of failure data.

This study investigated electrical characteristics and stability variations of amorphous indium gallium zinc oxide thin film transistors (a-IGZO TFTs) with plasma damage on their source/drain (S/D) regions. The influence of the plasma damage on the TFT performance is absent as the channel length is 36–100 μm. When the channel length is decreased to 3–5 μm, the mobility () of the bottom gate TFT (BG TFT) with plasma damage is significantly degraded to 0.6 cm2 (V s)−1, which is much lower than 4.3 cm2 (V s)−1 of a damage-free BG TFT. We utilized the TFT passivation layer and the indium tin oxide (ITO), which was used as the pixel electrode material in the TFT backplane, to be the top gate insulator and top gate electrode of the defective BG TFT to obtain the defective dual-gate TFT. The mobility can be restored to 5.1 cm2 (V s)−1. Additional process steps are not required. Besides, this method is easily implemented and is fully compatible with TFT backplane fabrication process. The transfer curves, hysteresis characteristics, stabilities under constant voltage stress and constant current stress tests were measured to give evidences that the traps created by the plasma damage on the S/D regions indeed can affect electron transport. This trap-limited conduction can be improved by using the top gate. It was proven that the top gate was not for contributing an observably additional current. It was for inducing electrons to electrically passivate the plasma-induced defects near the back channel. Thus, the trapping/detrapping of the electrons transporting in the front channel can be reduced. The trap density near the Fermi level, hopping distance and hopping energy are 1.1 × 1018 cm−3 eV−1, 162 Å, and 52 meV for the BG TFT with plasma damage on the S/D regions.

Characterization of Al2O3–HfO2–Al2O3 sandwiched MIM capacitor under DC and AC stresses

The key methods used to convert ramped voltage test (RVT) data to long term reliability measurement data are reviewed. During the last years the discussion to replace time consuming constant voltage stress (CVS) tests with ramp testing was pushed forward, mainly due to time constraints during qualification of high-k and also low-k material as well as through results obtained for ultrathin oxides [1]. The aim of this work is to contribute to the discussion with focus on thicker oxides used for automotive applications. While a future fWLR standard currently under discussion should also clearly state applicable oxide thickness ranges, advantages and limitations of various approaches, the principle assumptions and formulas are compared and applied to different data sets with gate oxide thicknesses of 9, 10, 17 and 50 nm, respectively. The results are then analyzed, discussed and compared to work based on material with much thinner/thicker oxides.

The electrical characteristics and reliability of the aluminum oxide (Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) metal-oxide-semiconductor (MOS) capacitors were investigated under low-temperature process consideration. The simple cost-effective technique in preparing the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> bilayer structure as the high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> gate dielectrics was demonstrated in this paper. SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> was prepared by room-temperature anodic oxidation, and Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> was fabricated by room-temperature in situ natural oxidation during the dc sputtering of aluminum in Ar/O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ambient. Compared to the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> MOS capacitors without nitric acid (HNO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) compensation, significant improvements in electrical characteristics, reliability, and uniformity were achieved by utilizing HNO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> to moderately oxidize the existing Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> layer. In addition, the charge trapping behaviors of our samples were also studied by time-dependent dielectric breakdown under the 1000-s constant voltage stress and constant current stress tests. It was found that the electron trapping is dominant under a low negative bias stress. However, under a high negative bias stress, the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> MOS capacitors show hole trapping due to the impact ionization near the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si interface. The in situ oxidation in sputtering with HNO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> compensation is suitable for future low-temperature dielectric applications.

ABSTRACTMOS capacitor composed of nc-CdSe embedded ZrHfO high-k gate dielectric stack was fabricated and characterized for nonvolatile memory functions. Detailed material and electrical properties have been investigated. With a large charge trapping capability, this kind of device can trap electrons or holes depending on the polarity and magnitude of the applied gate voltage. For the same stress time, the device trapped more holes than electrons under the same magnitude of gate voltage but different polarity. The negative differential resistance peak was observed at the room temperature due to the Coulomb blockade effect. The charge trapping mechanism was delineated with the constant voltage stress test. After 10 years of storage, about 56% of trapped charges still remain in the device.

This paper investigates the recoverable degradation of GaN-on-GaN vertical transistors under positive gate bias stress. Based on combined pulsed measurements and constant voltage stress test, we demonstrate the following original results: 1) when subjected to moderate gate stress (0 V <; V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> <; 3 V), the devices show a negative threshold voltage shift, which is correlated with a decrease in on-resistance. This process is ascribed to the detrapping of electrons from the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> insulator, induced by a low positive bias and 2) for high stress bias(V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> ≥ 5 V), a strong positive shift in threshold voltage is observed. This effect, which shows a slow recovery, is ascribed to the injection of electrons from the accumulation region (channel) toward the dielectric. Temperature-dependent measurements and 2-D simulations were carried out to support the hypothesis on degradation, and to evaluate the contribution of surface and bulk current in the n-GaN drift layer.

MoS2 has been reported to exhibit a resistive switching phenomenon in a vertical metal–insulator–metal (MIM) structure and has attracted much attention due to its ultra-thin active layer thickness. Here, the resistance evolutions in the high resistance state (HRS) and low resistance state (LRS) are investigated under constant voltage stress (CVS) or constant current stress (CCS) on MoS2 resistive switching devices. Interestingly, compared with bulk transition metal oxides (TMO), MoS2 exhibits an opposite characteristic in the fresh or pre-RESET device in the “HRS” wherein the resistance will increase to an even higher resistance after applying CVS, a unique phenomenon only accessible in 2D-based resistive switching devices. It is inferred that instead of in the highest resistance state, the fresh or pre-RESET devices are in an intermediate state with a small amount of Au embedded in the MoS2 film. Inspired by the capability of both bipolar and unipolar operation, positive and negative CVS measurements are performed and show similar characteristics. In addition, it is observed that the resistance state transition is faster when using higher electric stress. Numerical simulations have been performed to study the temperature effect with small-area integration capability. These results can be explained by a modified conductive-bridge-like model based on Au migration, uncovering the switching mechanisms in the ultrathin 2D materials and inspiring future studies in this area.

&#x0D; &#x0D; &#x0D; &#x0D; In this study, we revisit the concept of classical capacitor theory-and derive possible new explanations of the definition charge stored in a capacitor. We introduce the capacity function with respect to time to describe the charge storage in a classical capacitor and a fractional capacitor. Here we will describe that charge stored at any time in a capacitor as ‘convolution integral’ of defined capacity function of a capacitor and voltage stress across it which comes from causality principle. This approach, however, is different from the conventional method, where we multiply the capacity and voltage functions to obtain charge stored. This new concept is in line with the observation of charge stored as a step function and the relaxation current in form of impulse function for ‘ideal geometrical capacitor’ of constant capacity; when an uncharged capacitor is impressed with a constant voltage stress. Also this new formulation is valid for a power-law decay current that is given by ‘universal dielectric relaxation law’ called as ‘Curie von-Schweidler law’, when an uncharged capacitor is impressed with a constant voltage stress. This universal dielectric relaxation law gives rise to fractional derivative relating voltage stress and relaxation current that is formulation of ‘fractional capacitor’. A ‘fractional capacitor’ we will discuss with this new concept of redefining the charge store definition i.e. via this ‘convolution integral’ approach, and obtain the loss tangent value. We will also show how for a ‘fractional capacitor’ by use of ‘fractional integration’ we can convert the fractional capacity a constant that is in terms of fractional units (Farads per sec to the power of fractional number); to normal units of Farads. From the defined capacity function, we will also derive integrated capacity of capacitor. We will also give a possible physical explanation by taking example of porous and non-porous pitchers of constant volume holding water and thus, explaining the various interesting aspects of classical capacitor and a fractional capacitor that we arrive with this new formulation; and also relates to a capacitor breakdown theory-due to electrostatic forces.&#x0D; &#x0D; &#x0D; &#x0D; &#x0D;

Investigation of the influence of ramped voltage stress on intrinsic tbd of MOS gate oxides

The stress-induced leakage current (SILC) degradation of partially depleted silicon in insulator (PDSOI) devices under constant voltage stress (CVS) was studied. Firstly, the behaviors of threshold voltage degradation and SILC degradation of H-gate PDSOI devices under constant voltage stress were studied. It was found that both the threshold voltage degradation and SILC degradation of the device are power functions of the stress time, and the linear behavior between SILC degradation and threshold voltage degradation is good. Secondly, the soft breakdown characteristics of the PDSOI devices were studied under CVS. Thirdly, the effects of different gate stresses and different channel lengths on the threshold voltage degradation and SILC degradation of the device were studied. The results showed SILC degradation of the device under positive CVS and SILC degradation of the device under negative CVS. The shorter the channel length of the device was, the greater the SILC degradation of the device was. Finally, the influence of the floating effect on the SILC degradation of the PDSOI devices was studied, and the experimental results showed that the degree of SILC degradation of the floating device was greater than that of the H-type grid body contact PDSOI device. This showed that the floating body effect can exacerbate the SILC degradation of PDSOI devices.

In this paper, degradation behaviors of short channel high-klmetal gate p-FinFETs under hot carrier stress (HCS) and constant voltage stress (CVS) were compared to clarify the coupling ratio of NBTI component in hot carrier degradation (HCD). A discharge-based multi-pulse (DMP) technique was carried out to accurately analyze the energy distribution of interface trap and bulk trap under different stress conditions. Experiments show that the threshold voltage shift under CVS is about 3 times larger than that under HCS with the same stress bias. For both HCD and NBTI, the bulk hole trapping is dominant.

This work integrated a 3D high density (HD) and high aspect ratio(>30) cylinder MIM capacitor in Si interposer with 3 to 5 BEoL Cu layers (Min. width/space is <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.36/0.36\ \mu\mathrm{m}$</tex> for each layer within 1X Reticle) for 2.5D advanced packaging applications. The characterization of 3D HD capacitor with high capacitance density ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&lt; 18\ \mu\mathrm{F}/\text{mm}^{2}$</tex> ), high distributed compatibility (>40% interposer area), and low leakage ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.1\ \text{pA}/\mu\mathrm{m}/\text{mm}^{2}$</tex> under 2V at 25°C) is benefit to power integrity design. Comparing to typical integrated passive device (IPD) which is bonded at substrate landside, this work proposed a kind of monolithic 3D HD Capacitor and Si wafer technique. The Si interposer is consisted of through-silicon-via (TSV), fine pitch re-disturbing layer (RDL) and 3D HD capacitor can be a good chip substrate solution for high-performance and high-frequency application in artificial intelligent (AI), high performance computing (HPC), and System in package (SIP) region.

The conduction mechanism of stress induced leakage current (SILC) through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress (CVS). The simulation results show that the SILC is formed by trap-assisted tunnelling (TAT) process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.