Microcode simulation in the computer architecture course

This paper traces the history of computer architecture courses in electrical engineering departments. Previously unpublished data from the Fall 1972 COSINE survey are given to show current computer architecture course offerings and texts. Computer architecture courses offered in 1972-73 are analyzed, compared with ACM and COSINE recommendations, and classified into five categories: introductory computer engineering courses with a computer architecture flavor, software-oriented computer organization courses, hardware-oriented computer organization courses, case study courses, and topical seminars. Future trends in computer architecture education are predicted.

This study examined the effectiveness of MOOC in the blended learning of Computer Architecture and Organization course based on the integration of online learning using MOOC and face-to-face learning.Specifically, the aim of the study was to identify factors that could influence student acceptance of MOOC in terms of immersion (IM) and intention to use (BIU) based on the HMSAM. Methodology:Quantitative approach through pre-test/post-test control group design was implemented in this study.Simple random sampling was carried out to recruit the study sample comprising 168 undergraduates from a population of 298 students.Pearson correlation analysis, ANOVA and multiple regression analysis were performed on the survey data collected using online questionnaire.Main Findings: Joy, control, perceived usefulness (PU) and curiosity were significantly correlated with IM while PU, joy and curiosity were significantly correlated with BIU.Control, PU, joy and curiosity were significant predictors of student acceptance in terms of IM and BIU.33% of IM variances and 22% of BIU variances can be predicted by control, PU, joy and curiosity.Applications of this study: This study is useful in educational technology area where it shows that MOOC is a potent platform for blended learning, but its effectiveness relies on appropriate division of learning between online and face-to-face mode.Therefore the study on teaching and learning strategies, techniques and tools are widely open in order to improve the effectiveness of blended learning in the future.Novelty/Originality of this study: The finding suggests that the proportion of learning based on online and face-to-face mode should be carefully apportioned where the effectiveness of MOOC in the blended learning was significantly lower if it was used up to 71% and the effectiveness will be increased if only 29% of MOOC was used in the non-blended learning.

The MIPS computer architecture is widely used in undergraduate computer architecture and organization courses because of its straightforward design. MIPS is the primary example of the popular textbook Computer Organization and Design [2], used at over 400 universities. We describe a GUI, Java-based simulator for the MIPS assembly language, with characteristics that emphasize usefulness to undergraduate computer science students and - importantly - their instructors.Java and Sun are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries.

Cache memories represent a core topic in all computer organization and architecture courses offered at universities around the world. As a consequence, educational proposals and textbooks address important efforts to this topic. A valuable pedagogical help when studying cache memories is to perform exercises based on simple algorithms, which allow the identification of cache accesses, for instance, a program accessing the elements of an array. These exercises, referred to as code-based exercises, have a good acceptance among instructors of computer organization courses. Nevertheless, no tool (e.g., simulator) has been developed to be used in undergraduate courses working with this kind of exercises; therefore, students perform such exercises by means of the classic paper and pencil methodology. To fill this gap, this paper proposes a new pedagogical tool, namely Spim-cache. A laboratory example is also presented for illustrative purposes.

The Digital Logic and Computer Architecture related courses are one of the key knowledge areas in Computer Science (CS) used to enhance students' understanding of Boolean algebra, logic gates, registers, arithmetic logic units, etc. and provides insights how software and hardware are related in a computing system. Experimental Centric based Instructional Pedagogy (ECP) with portable laboratory instrumentation might provide real hands-on experience to obtain a practical understanding of the concepts at a lower cost compared to virtual hands-on laboratories. This paper presents the initial adaptation of an evidence-based, experiment-focused teaching approach to introduce the fundamentals of digital logic concepts using the commercial ADALM 1K Active Learning Module in a Computer Architecture course for the first time in the CS department at a university serving predominantly minority students. To evaluate the impact of the ECP on student performance in the Computer Architecture course, we conducted three different evaluations, which are class observation, signature assignment, and the Motivated Strategies for Learning Questionnaires (MLSQ) survey. The results of the Classroom Observation Protocol for Undergraduate STEM (COPUS) show more student engagement when ECP is implemented; the output of the signature assignment shows an increase in students' learning outcomes; and the MLSQ survey, which tests the students' motivation, critical thinking, curiosity, collaboration, and metacognition, ascertains the effect of the ECP on the CS students who participated in the experiment.

Most computer architecture courses are geared toward the classical von Neumann style of computer architectures, mentioning only in passing other models such as data flow computation. This is unfortunate, due to the high degree of parallelism possible using data flow. We present an alternative course, designed as an elective in computer architecture for upper level undergraduate or graduate students, that presents a side-by-side comparison of von Neumann and data flow architectures.Our teaching environment is based on Simple Arithmetic SISAL (SAS), a subset of the applicative programming language SISAL, which we designed for both teaching about and research into data flow architectures. SAS runs in a highly integrated environment, allowing students to implement their program on a von Neumann architecture, then observe its execution through a data flow simulator. The environment runs on a standard IBM-style personal computer, providing a cost-effective platform for presenting the course.

This paper describes our experiences with closed laboratories in a computer architecture course and highlights the development of a capstone project. We advocate the use of software as a cost effective means of supporting analysis, design, and experimentation. Improvements to the course in regards to content, environment for learning, student perception, skills accomplished and retained, and instructor involvement are outlined. Several labs are summarized, including the capstone project tying together all aspects of machine organization. We conclude that integrating design education into computer science with the logic simulator lab approach is worthy of our continued efforts.

Introductory-level computer architecture courses often rely on programs with a graphical user interface (such as Logisim) for processor design projects. While these tools provide an easy introduction into logic design, they can detach students from real-world design constraints such as ISA standard tests, and real-world ramifications such as timing and area. This paper introduces a testing flow based on open-source tools that allows Logisim-based designs to be built into ISA-test-compatible simulation binaries, synthesized into gate netlists, and compared for similarity. This flow was used in UC Berkeley's fall 2020 Great Ideas of Computer Architecture course; out of 695 project submissions, over 96% achieved highly-functional designs as measured by the presented infrastructure. CCS CONCEPTS •Social and professional topics $\rightarrow$ Computer engineering education; •Computer systems organization $\rightarrow$ Reduced instruction set computing; Pipeline computing. ACM Reference Format: Ryan Lund, Connor McMahon, Dan Garcia, and Borivoje Nikolić. 2021. Improved Processor Design Project Testing. In Proceedings of WCAE '21. ACM, New York, NY, USA, 7 pages. https://doi.org/10.1145/1122445.1122456

Teaching cases integrated with ideological and political elements serve as crucial carriers for realizing knowledge transmission, ability training, and value shaping. In response to the new requirements of ideological and political teaching reform in the Principles of Computer Organization course, this paper introduces the BOPPPS teaching model embedded with ideological and political elements, expounds on the overall ideological and political objectives of the Computer Organization course, and takes the teaching of "Read-Only Memory" in this course as a concrete example. It details the design of an ideological and political teaching case for read-only memory, which centers on "paying attention to the domestic and foreign research progress of USB flash drives and flash memory chips". The case aims to achieve the synchronous development of knowledge teaching, ability training, and value guidance, thereby promoting the construction of ideological and political education in the Computer Organization course and providing reference value for peers in the field.

While substantial research has demonstrated that active learning pedagogies are better for learning than passive lectures, we need to understand the trade-offs between different active learning pedagogies. Computer Architecture at Midwestern University has historically been taught using active lectures, introducing content with a few clicker questions. In Fall 2018 (N = 363), short video lectures were made available to students as a supplemental resource. In Spring 2019, the instructor flipped the course, requiring students to watch the video lectures and complete an assignment before attending class. Two versions of the course were taught concurrently, using the same homework assignments, machine problems, and examinations but with different in-class pedagogies. Version SP19PI (N = 179) was taught using peer instruction. Version SP19CP (N = 73) was taught using collaborative problem solving, organizing students into teams of 3 to work on problems. Students completed surveys that measured their perceptions of time spent on the course, course difficulty, perceptions of stress, and sense of belonging. We compare students' performance on midterm exams and their non-cognitive outcomes to examine the relative effects of these different active learning pedagogies. We find that both flipped offerings (peer instruction and collaborative problem solving) benefited students beyond active lectures. Peer instruction (SP19PI) made learning more efficient. Collaborative instruction (SP19CP) provided greater social support for learning and eliminated gender grade disparities.

This Innovative Practice Full Paper presents a framework for generating computer-based exams for complex engineering systems (such as cache memories) that can be machine graded while still offering partial credit for students. Complex multi-faceted engineering systems often require long, multi-part problems to fully assess students’ understanding of those systems. Cache memories represent one such system in computer architecture courses. Traditionally, we assessed students’ understanding of caches using comprehensive, multipart questions in a paper-based exam. Grading these exams was time-consuming and relied on subjective grading. To cope with rising enrollment, we sought to address these issues by developing machine administered and gradable exams that did not heavily rely on multiple-choice questions or exact numerical responses. Additionally, this system needed to provide partial credit, a common expectation of our students. We developed a cache simulator to use as a back-end for our questions. We used the simulator to develop exam questions and new homework assignments to help students practice cache memory concepts. To give students access to fair partial credit, we allowed multiple submissions for the exam questions with limited feedback. We also awarded partial credit for answers within certain tolerance of the correct answer. The partial credit awarded reduced as deviation from the correct answer increased. Consequently, students could correct minor mistakes or propagating errors which are common reasons for awarding partial credit. To evaluate the effect of the switch from paper-based to computerized exam, we ported questions from one of our paper-based exams to a computerized exam. We evaluated the differences in student performance on paper-based version and the computerized version of the questions and found mixed results with students performing comparably or better than the paper-based exam on the computer-based exam. We also surveyed students about their experience with the computer-based exam. Students overwhelmingly indicated a preference for the computer-based exam. We believe that ideas from our work can be used to automate generation, administration, and grading of complex multi-part questions in engineering disciplines beyond computer architecture.

We present a new learning method of microprocessor architecture based on design and verification using functional simulation. Our main goals are to improve and optimize the learning process, motivating students to study and learn theoretical and practical aspects of microprocessor architecture, using functional simulators to validate the microprocessor design and to construct knowledge; and develop research activities during an undergraduate course. Our method is based on learning, constructivism theory, problem based learning, group projects, design of academic microprocessors as motivation for theory study/learning and verification of designed microprocessors through functional simulators developed by students. To validate the proposed method we analyze two microprocessors and functional simulators: a digital signal processor using ASIP and RISC concepts, and a RISC ASIP home automation processor. They were developed in a computer architecture course (computer science, PUC-Minas, Brazil) as the application of this method. In the conclusion students and professor analyze the results, highlighting the main differences, advantages and disadvantages of the new method.

Computer organization course is the fundamental course in computer science and engineering. It is also the core course of the undergraduate degree program of College of Computer Science at Zhejiang University. It is important that how to provide supplementary teaching resources and methods to improve the teaching effect. In this paper, we present a Top-Down and Bottom-Up blended teaching model and the supplementary online system for the computer organization course. This new model consists of multi-level online system for the teaching. The feedback from students shows that the teaching model and the online system are satisfactory.

Students learn better when they both hear and do. In computer architecture courses “doing” can be difficult in small schools without hardware laboratories hosted by computer engineering, electrical engineering, or similar departments. Software solutions exist. Our success with George Mills' Multimedia Logic (MML) is the focus of this paper. MML provides a graphical computer architecture solution with convenient I/O support and the ability to build and emulate a variety of computer designs. It has proven highly motivational to upper division computer science students designing and constructing emulated computers. Student projects resulted in excellent student understanding of the detailed inner workings of computers. Students also developed better teamwork skills and produced useful training aids for the lower division computer organization class. Designs implemented include 8 bit and 16 bit von Neumann and Harvard architectures, from single cycle to 12 cycle instructions. Issues resolved during the learning process include timing, initialization, instruction set architecture, and I/O and assembler design. We discuss pedagogical issues involved in using MML to implement instructor and student computer designs. MML is compared to using a hardware-based Intel 8085 microprocessor basic systems course.

This paper describes the undergraduate computer architecture courses and laboratories introduced at Georgia Tech during the past two years. A core sequence of six required courses for computer engineering students has been developed. In this paper, emphasis is placed upon the new core laboratories which utilize commercial CAD tools, FPGAs, hardware emulators, and a VHDL based rapid prototyping approach to simulate, synthesize, and implement prototype computer hardware.