Minimization of passive circuits losses realized on low resistivity silicon using micro-machining techniques and thick polymer layers

This paper presents experimental results for line-to-line coupling between adjacent coplanar waveguide (CPW) transmission lines. The CPW lines are fabricated on glass and low resistivity CMOS grade Si substrates coated with a 20/spl mu/m cyclotene polymer. From the measurement results it is found that the coupling increases with frequency on low resistivity silicon substrate while the coupling on glass shows relatively constant peaks. A spacing of 600/spl mu/m between CPW lines is required to avoid parasitic coupling less than 30dB for frequencies up to 30GHz when fabricated on low resistivity silicon, while a spacing of 200/spl mu/m is required when fabricated on glass. The conductor width (W) and the slot width (S) for low resistivity silicon is 80/spl mu/m and 45/spl mu/m, and on the glass substrate W = 150/spl mu/m, S = 30/spl mu/m. Based on full-wave EM simulation results, it is argued that the primary coupling mechanism is through the interaction of higher-order modes.

This paper deals with a novel technological solution based on the use of surface micromachining in coplanar slots that are filled with a thick organic dielectric layer. This technique enables both Q factor and losses improvements of passive circuits realized on low resistivity silicon substrate. It permits indeed to achieve much better attenuation level without an important decrease of the effective permittivity.

The properties of transmission lines on low-resistivity silicon substrate (/spl rho/=10 /spl Omega/.cm) are investigated. Coplanar lines on silicon substrate with a 10 /spl mu/m dielectric film show that losses of 0.6 dB/mm can be obtained at 50 GHz. A new embedded ultra-low loss coplanar line is proposed, with a broad interval of characteristic impedance.

In this paper, technological solutions based on the use of thick low-k polymer layers on low-resistivity (LR) silicon substrate have been investigated. These thick organic layers provide an insulation of interconnects and passives circuits from the lossy silicon substrate and thus minimize its dramatic impact on the performances. Different thicknesses of polymer layer have been tested. Both EM-simulations and high-frequency characterizations have shown an important benefit in coplanar waveguide performances by employing a large polymer thickness (30 /spl mu/ in our case). A noticeable increase of the Q-factor close to 16% has been achieved with burying the realized CPW lines into a quasi-homogeneous polymer medium.

: This report contains information on the items of equipment acquired with this DURIP award including name. cost, manufacturer and special circumstances regarding their acquisition. It also contains a summary of each research project on which the equipment has been and will be used. These projects are of major significance to the Department of Defense and include topics such as reconfigurable tuners and band-stop filters using MEMS switches, micromachined cavity diplexers and loaded cavity resonators, reconfigurable electromagnetic bandgap resonators and microwave circuits on low resistivity silicon substrates. A list of associated publications is also provided.

This paper reports the design, fabrication, electrical characterization and packaging of micromachined shunt capacitive switch with low actuation voltage. These switches are fabricated on a low resistive silicon substrate using only a four mask surface micromachining process. The co-planar waveguide is patterned using chrome/gold layer. Positive photoresist S1813 is used as the sacrificial layer. The top beam membrane is made of gold. The membranes are released through a wet release process through Piranha solution. Supercritical point drying tools were used for the top beam release after wet etching to provide anti-stiction. The switches are 300 µm long with 10 μm holes on the top membrane to lower both residual stress and pull-in voltages. These switches exhibit low actuation voltages in the range of 5.5–6.4 V. The RF characterization shows that these switches have low insertion loss and high isolation in the frequency range of interest. The packaging was carried out using commercially available surface mount style RF packages. However, the whole packaging process is performed under low temperature in order to free the MEMS structures of thermally induced stress which otherwise would affect the performance of the switch. The adhesion of the die to the bottom package is excellent and is tested by die shear test. The packaged switch has passed the non-destructive pull test.

We combine a scanning near-field microwave microscope with an atomic force microscope for use in localized thin film dielectric constant measurement, and demonstrate the capabilities of our system through simultaneous surface topography and microwave reflection measurements on a variety of thin films grown on low resistivity silicon substrates. Reflection measurements clearly discriminate the interface between approximately 38 nm silicon nitride and dioxide thin films at 1.788 GHz. Finite element simulation was used to extract the dielectric constants showing the dielectric sensitivity to be Deltaepsilon(r)=0.1 at epsilon(r)=6.2, for the case of silicon nitride. These results illustrate the capability of our instrument for quantitative dielectric constant measurement at microwave frequencies.

A micromachining process has been developed to create high impedance and low loss high aspect ratio coplanar waveguide (HARC) on low resistivity silicon. The process uses silicon DRIE to create an array of tall mesas that are spaced with a precise pitch. The silicon mesa array is then merged into a single solid SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> mesa using thermal oxidation. The solid SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> mesa creates a wide dielectric for use in high impedance HARC. The complete fabrication process includes DRIE, thermal oxidation, electroplating, planarization, and substrate removal to create HARC on low resistivity silicon with a planar surface. A high impedance HARC has been fabricated on silicon using this method. Measurements show that silicon substrate removal increases the line impedance from 20 Ω to 57 Ω, reduces effective dielectric constant from 6 to 2, and reduces attenuation constant from 33 dB/cm to 4 dB/cm @ 30 GHz. Measurements are compared to an analytical model derived for HARC.

In this chapter, a circularly polarized on-chip antenna (OCA) is designed on a low resistivity silicon (Si) wafer by considering standard CMOS technology. The lossy electrical properties of Si are not suitable for the design of OCA and responsible for its gain reduction. The proposed OCA achieved the significant gain enhancement of +22.15 dB by using micromachining technique. The OCA resonates at 1.26 GHz and covers complete L-band. The size of OCA is miniaturized up to \( \lambda _{0} \)/15.8 \( \times \) \(\lambda _{0} \)/23.8 mm\( ^{2} \) by using two double diamond shaped symmetrical slots on the patch. These slots not only miniaturized the antenna size but also provided the circular polarization for the OCA. The OCA shows a bandwidth (BW) of 1.7 GHz (BW < 10 dB) and axial ratio (AR) bandwidth of 4.3% (AR < 3 dB) from 1.23–1.30 GHz range. All the simulated results and corresponding figures have been thoroughly explained in various sections of this chapter.

This paper presents the fabrication process of a thin suspended membrane on normal low resistivity silicon (LRSi), which is then utilized to design millimeter-wave (mm-wave) transmission line and passive circuits with low loss. First, two redistribution metal layers are formed on a plain LRSi wafer with benzocyclobutene in-between. Then, the wafer is thinned down and etched from backside with a specific pattern. Based on this process, a volume is introduced underneath the front side structure and the lossy LRSi substrate is replaced by air, which is the ideal substrate with no loss. Using this method, the substrate loss that contributes the majority part of total loss in mm-wave circuits on LRSi is eliminated. As the operating frequency goes into mm-wave region, the circuit size is scaled down so that the suspended portion is so small that it will not increase the mechanical instability of the structure. Therefore, the proposed suspended membrane on LRSi technology provides an excellent platform to construct mm-wave components. A U-shaped slotline resonator formed on the first redistribution layer is proposed and its quality factors are studied in detail. A second-order bandpass filter is designed and implemented by cascading two such U-shape slotline resonators. The measured frequency responses exhibit good filtering performance, with fractional bandwidth of 13.9% at 126.8 GHz, midband insertion loss of 3.9 dB and passband return loss larger than 14.2 dB. It demonstrates that the proposed suspended membrane on LRSi technology is an excellent candidate for designing low loss mm-wave components.

The measured photocurrents from two different p-n-junction silicon photodiodes at 170-Å (73-eV) and at 8.34-Å (1480-eV) light are presented. One is a standard extreme-UV photodiode fabricated on low resistivity silicon (70-100 Ω cm), and the other is fabricated on high-resistivity silicon (> 2 × 10(4) Ω cm). The photocurrents from the diode on high-resistivity silicon are at least an order of magnitude greater than the photocurrents from the diode on low-resistivity silicon when a reverse bias of 40 V is applied to each. This photocurrent enhancement is 15.4 ± 4 at 8.34 Å and 12.5 ± 2 at 170 Å.

This paper describes fabrication, characterization and simulation of low-loss coplanar waveguide (CPW) interconnects on low-resistivity silicon substrate. The fabrication of CPWs is low-temperature (below 250/spl deg/C) and incorporates a spin-on low-k dielectric benzocyclobutene (BCB) and self-aligned electroplating of copper. The performance of CPWs is evaluated by high-frequency characterization and EM simulation. CPWs with different line width (W) and line spacing (S) are investigated and compared. Using a BCB layer as thick as 20 /spl mu/m, CPW fabricated on a low-resistivity silicon substrate exhibits an insertion loss of 3 dB/cm at 30 GHz.

The emphasis on high aspect ratio micromachining techniques for microsystems/MEMS has been mainly to achieve novel devices with, for example, high sensing or actuation performance. Often these utilize deep structures (100–1,000 μm) with vertical wall layers but with relatively modest spatial resolution (1–10 μm). As these techniques move from research to industrial manufacture, the capital cost of the equipment and the cost of device manufacture become important, particularly where more than one micromachining technique can meet the performance requirements. This paper investigates the layer-processing costs associated with the principal high aspect ratio micromachining techniques used in microsystems/MEMS fabrication, particularly silicon surface micromachining, wet bulk etching, wafer bonding, Deep Reactive Ion Etching, excimer laser micromachining, UV LIGA and X-ray LIGA. A cost model (MEMSCOST) has been developed which takes the financial, operational and machine-dependent parameters of the different manufacturing techniques as inputs and calculates the layer-processing costs at the wafer and chip level as a function of demand volume. The associated operational and investment costs are also calculated. Cost reductions through increases in the wafer size and decreases in chip area are investigated, and the importance of packaging costs demonstrated.

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper reports the theoretical and experimental studies of high-<formula> <tex>$Q$</tex></formula> suspended microinductors produced by flip-chip assembly for multigigahertz RF integrated-circuit applications. The effects of device and substrate parameters on the <formula formulatype="inline"><tex>$Q$</tex> </formula> factor of the inductor devices are studied by numerical simulation using Ansoft's High Frequency Structure Simulator electromagnetic field simulation package. Suspended inductor devices are realized using a flip-chip assembly method in which the inductor structures with the supporting pillars are fabricated on a low-cost polyimide thin-film carrier and then assembled onto a low resistivity (3–4 <formula formulatype="inline"><tex>$\ \Omega\,\cdot\,$</tex></formula>cm) silicon substrate by flip-chip bonding. Individual and 2<formula formulatype="inline"> <tex>$\,\times\,$</tex></formula>2 arrays of meander and spiral inductor designs have been successfully fabricated with air gap heights ranging from 15 to 31 <formula formulatype="inline"><tex>$\mu$</tex></formula>m. Maximum <formula> <tex>$Q$</tex></formula> factors of <formula formulatype="inline"><tex>${\sim}$</tex> </formula>15 and <formula formulatype="inline"><tex>${\sim}$</tex></formula>13 at <formula formulatype="inline"><tex>${\sim}$</tex></formula>1 GHz have been achieved for meander and spiral suspended inductor devices before pad deembedding. It is shown that the optimal air gap between the inductor and substrate surface is <formula formulatype="inline"><tex>${\sim}{\hbox{15}}\ \mu$</tex></formula>m beyond which no further enhancement in the <formula formulatype="inline"> <tex>$Q$</tex></formula> factor can be obtained for devices on low-resistivity substrates. The experimental results are in excellent agreement with that of theoretical simulation. The inductor assembly method requires minimal chip/wafer processing for integration of high-<formula><tex>$Q$</tex></formula> inductors. </para>

A novel silicon-based suspended MIM capacitor fabrication technique combining thin-film and bulk silicon etching technologies with high-quality factor is presented. The influence of low resistive silicon on the parasitics of integrated capacitors is analyzed by EM simulation. The suspended structure is achieved and optimized by a two-step back-etching process. The Q factor of the 3.3 pF suspended MIM capacitor at 2 GHz is about 79% larger than the non-suspended one and the Q max is increased from 46.8 to 61.9, respectively. And a ten-element π equivalent model including electrode and substrate parasitics as well as dielectric loss is used to fit the suspended MIM capacitors well up to 10 GHz, demonstrating that the suspended MIM capacitors exhibit both lower substrate loss and lower parasitic capacitance of the substrate.