Minimum energy point tracking based on adaptive voltage scaling circuit

With feature size scaling, the supply voltage of digital circuits is becoming lower and lower. As a result, the supply voltage of analogue and RF circuits must also be reduced for system on chip (SoC) realisation. This article proposes an ultra-low-supply voltage-controlled oscillator (ULSVCO) and designs a sigma–delta fractional-N frequency synthesiser which adopts such ULSVCO. A mathematical phase-noise model is built here to describe the noise performance of the low-supply voltage-controlled oscillator (VCO). The substrate of the cross-coupled NMOSFETs in the proposed ULSVCO is not grounded but connected to the supply to further reduce the supply voltage. Implemented in 0.18 μm CMOS technology, the proposed ULSVCO can be operated at a supply voltage as low as 0.41 V, the central frequency is set to 1.55 GHz, the phase noise is −116 dBc/Hz@1.0 MHz. The minimum supply voltage is decreased by about 11% after our idea is adopted and the power consumption of the ULSVCO is only 1.04 mW. With the proposed ULSVCO, we design a sigma–delta-modulator (SDM) fractional-N phase-locked loop frequency synthesiser, which has a 1.43–1.75 GHz frequency tuning range. When the loop bandwidth is set to 100 KHz, the phase noise of our PLL is −110 dBc/Hz@1.0 MHz.

This paper presents a fully integrated solar energy harvester for ultra-low power autonomous microsystems. This area- and power-efficient circuit harvests solar energy from a micro-power photovoltaic module to charge a rechargeable NiMH microbattery. As the harvested solar energy varies considerably in different lighting condition, the proposed circuit scales the power consumption and performance of the target microsystem, according to the harvested solar energy. Battery voltage is measured when battery is discharged by a high discharge current, to estimate harvested solar energy. Operating frequency and supply voltage of digital circuits and bias currents of analog circuits are reconfigured dynamically, based on measured battery voltage to optimize power-performance of the microsystem. This circuit occupies a core area of only 0.2mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a 0.18μm CMOS process and features a low power consumption of 390nW operating at its highest clock frequency.

This paper refers to an optimal pair of the supply and the threshold voltages, which minimizes the energy consumption under the given delay constraint, as a minimum energy point (MEP). This paper proposes an approximation-based implementation method for an MEP tracking algorithm over a wide operating performance region. The key point is that the accuracy required for determining the MEP is not high. Even if the MEP estimated by the algorithm differs by a few tens of millivolts in comparison with the actual MEP, the energy loss introduced by the estimation error is small. Therefore, the complexity for determining the MEP can be reduced by approximating complex operations such as the logarithmic or the exponential functions in the MEP estimation algorithm, which leads to hardware-Isoftware-efficient implementation. Measurement results based on a 32-bit RISC-V processor fabricated in a 65-nm process technology show that the energy loss introduced by the proposed approximation is less than 1% in comparison with the MEP operation. When the MEP tracking algorithm is implemented in software, the MEP estimation time is reduced from 1 ms to 13 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu \mathrm{s}$</tex> . When implemented in hardware, the proposed method can reduce the area of an MEP estimation circuit to a quarter.

The density functional theory was employed to investigate Eu(III) complexes with three beta-diketonates and two phosphine oxides (complex M1: Eu(bdk)3(TPPO)2, complex M2: Eu(bdk)3(TMPO)2, and complex M3: Eu(bdk)3(TPPO)(TMPO)) deemed to be the model complexes of the fluorescence compounds for the ultraviolet LED devices we have recently developed. For each complex, two minimum energy points corresponding to two different optimized geometries (structures A and B) have been found, and the difference of the energy between two minimum energy points is found to be quite small (less than 1 kcal/mol). Vertical excitation energies and oscillator strengths for each complex at two optimized geometries have been obtained by the time-dependent density functional theory, and the character of the excited states has been investigated. For complex M3, the absorption edge is red-shifted, and the oscillator strengths are relatively large. The efficiency of intersystem crossing and energy transfer from the triplet excited state to the Eu(III) ion is considered by calculating DeltaE(ISC) (the energy difference between the first singlet excited state and the first triplet excited state) and DeltaE(ET) (the difference between the excitation energy of the complex for the first triplet excited state and the emission energy of the Eu(III) ion for 5D to 7F).

Minimizing the energy consumption of battery-powered systems is a key focus in integrated circuit design. This paper presents an energy minimization loop, with on-chip energy sensor circuitry, that can dynamically track the minimum energy operating voltage of arbitrary digital circuits with changing workload and operating conditions. An embedded DC-DC converter which enables this minimum energy operation is designed to deliver load voltages between 0.25 V to 0.7 V. The minimum energy tracking loop along with the DC-DC converter and test circuitry were fabricated in a 65 nm CMOS process. The area overhead of the control loop is only 0.05 mm2. Measured energy savings of the order of 50%-100% are obtained on tracking the minimum energy point (MEP) as it varies with workload and temperature. The DC-DC converter delivers load voltages as low as 250 mV and achieved an efficiency >80% while delivering load powers of the order of 1 muW and higher from a 1.2 V supply.

In this report we introduce an iterative procedure for constructing a quasidiabatic Hamiltonian representing N(state)-coupled electronic states in the vicinity of an arbitrary point in N(int)-dimensional nuclear coordinate space. The Hamiltonian, which is designed to compute vibronic spectra employing the multimode vibronic coupling approximation, includes all linear terms which are determined exactly using analytic gradient techniques. In addition, all [N(state)][N(int)] quadratic terms, where [n]=n(n+1)/2, are determined from energy gradient and derivative coupling information obtained from reliable multireference configuration interaction wave functions. The use of energy gradient and derivative coupling information enables the large number of second order parameters to be determined employing ab initio data computed at a limited number of points (N(int) being minimal) and assures a maximal degree of quasidiabaticity. Numerical examples are given in which quasidiabatic Hamiltonians centered around three points on the C(3)H(3)N(2) potential energy surface (the minimum energy point on the ground state surface and the minimum energy points on the two- and three-state seams of conical intersection) were computed and compared. A method to modify the conical intersection based Hamiltonians to better describe the region of the ground state minimum is introduced, yielding improved agreement with ab initio results, particularly in the case of the Hamiltonian defined at the two-state minimum energy crossing.

Variability modeling in near-threshold CMOS digital circuits

This study aims at comparing two subthreshold flip-flop architectures in frequency divider applications, implemented and fabricated in 130 nm CMOS process technology. They are the Power PC (Performance Computing) and Nand race-free flip-flops. Identification of a reliable and power efficient flip-flop, used in a frequency divider for ultra-low supply voltages, has been verified by measurements. The simulated results based on a netlist extracted from layout show that upsizing the Power PC flip-flop increases it's reliability while it may still provide lower power consumption than the Nand race-free flip-flop. Based on results verified by measurements for ten chip samples, both frequency dividers have demonstrated functionality down to a V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</inf> of 135 mV. The Power PC flip-flop based frequency divider is 24% more energy efficient than the Nand race-free counterpart at an ultra-low supply voltage of 160 mV. The energy per operation for the Power PC- and Nand race-free- frequency dividers at the minimum energy point (MEP) of 250 mV, and maximum operating frequency, are 12.2 and 12.5 fJ, respectively.

Minimum energy per operation is typically achieved in the subthreshold region where low speed and low robustness are two challenging problems. This paper studies the impact of Back Biasing (BB) schemes on these features for FDSOI technology. We show that Forward BB can help cover a wider design space in term of optimal frequency of operation while keeping minimum energy. Asymmetric BB between NMOS and PMOS can mitigate the effect of systematic mismatch on Minimum Energy Point (MEP) and robustness. With optimal asymmetric BB, we achieve either a MEP reduction up to 18% or a 36× speedup at the MEP.

This paper introduces a transregional energy model to estimate the energy consumption of digital designs for voltages widely ranging from nominal down to deep sub-threshold. The model also predicts the optimal voltage at which the minimum energy point (MEP) occurs, and the resulting minimum energy achievable under aggressive voltage scaling. The model provides the energy profile versus voltage based on a few technology-dependent parameters that are extracted through simple circuit simulations, and other few design-dependent parameters extracted from synthesis or Place&Route reports at nominal voltage only. The model captures the effect of input-dependent (e.g., switching activity), technology-dependent (e.g., corner, transistor flavor), and micro-architectural parameters (e.g., logic depth). The model exhibits a typical error below 10%, and is well suited for design exploration under wide voltage scaling, as it avoids detailed and time-consuming multi-corner and multi-voltage iterations. Also, the model provides a quick estimate of the achievable MEP for a given design. Accordingly, the proposed model is a useful tool that supports early selection of the most energy-efficient design options to meet a targeted energy profile at low voltages.

We propose an original Technology/Design Co-optimization of standard cells mixing devices of different threshold voltages (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> -flavors) within a cell. It is successfully applied with nMOS Low-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> (LVT) and pMOS Super-Low-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> (SLVT) in Ultra-Low-Voltage (ULV) Fully Depleted Silicon-On-Insulator (FDSOI) LETI standard cells using diffusion breaks. It enables adjusting the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of pMOS subject to SiGe-channel-induced Local Layout Effect (LLE); leading experimentally to a 23% frequency gain on 22nm FDSOI technology for a 2-finger inverter Ring Oscillator (IVSX2 RO) vs. reference LVT at the same static leakage and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =0.4V supply voltage; which corresponds to the Minimum Energy Point (MEP). This solution is combined with Forward Body Biasing (FBB), which brings +253% frequency at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =0.4V and FBB=1.6V and improves the energy efficiency with a -13% minimum Energy Delay Product (EDP) along with a 50mV V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> reduction at the minimum EDP.

Scaling supply voltage to the Near-Threshold Voltage (NTV) region is an effective approach for energy-constrained circuit design at the cost of performance reduction. However, the impacts of process and runtime variations on the circuits operating at NTV aggravate due to the larger sensitivity to variations. This sensitivity changes the performance and power consumption of the circuit impacting the Minimum Energy Point (MEP). Therefore, finding an optimum operating voltage for Near-Threshold Computing (NTC) in a per-chip basis to account for variability is very challenging. In this paper, we propose a post-fabrication calibration approach based on machine learning in which the optimal supply voltage of each chip is determined during manufacturing test according to basic characteristics of the circuits such as dynamic and leakage power. Unlike the conventional approaches which find the MEP during runtime, the proposed technique imposes almost no overhead (area and power) to the circuit. The simulation results show a significant improvement (59.1%) in the energy efficiency compared to the state-of-the-art approaches.

Currently in deep sub-micron technologies such as 16 nm and smaller, requirement of portable devices focus designers' attention on low power design of CMOS circuits and systems, using different low power techniques, trying to decrease dynamic and/or leakage power. One of the widely employed power optimization methods is multi voltage design, used to reduce power by dividing IC into voltage IC domains. This paper presents a new approach of multi voltage design technique, generalizing it, to use “n” voltage domains with “n” different supply voltages, providing efficient power reduction of digital systems such as processor. Basically, voltage areas match sub modules of processor with addition of modified version of adaptive voltage scaling.

Building on previous theoretical and spectroscopic studies of the pyrazolyl radical, a new three-state quasidiabatic Hamiltonian is reported which reproduces not only the equilibrium geometries and harmonic frequencies of the nominal X (2)A(2) state and low-lying A (2)B(1) excited state, but also the minimum energy points on the lowest two-state (X (2)A(2), A (2)B(1)) and three-state (X (2)A(2), A (2)B(1), B (2)B(2)) seams of conical intersection. The three-state Hamiltonian includes all terms through second order in both the diagonal and off-diagonal blocks. Its construction is accomplished in two steps. First, a nascent Hamiltonian, centered at the lowest energy two-state conical intersection, is determined using ab initio gradients and derivative couplings. Then, the nascent Hamiltonian is improved by optimizing selected contributions to the second-order coefficients to better reproduce relevant minima and harmonic frequencies. This Hamiltonian is then expressed in a basis tailored to describe the neutral states of interest under the multimode vibronic coupling approximation. The vibronic Hamiltonian is diagonalized to obtain negative ion photoelectron spectra for pyrazolide-h(3) and the completely deuterated analog pyrazolide-d(3). The resultant spectra, determined employing vibronic Hamiltonians as large as 500 million terms, compare favorably to recent theoretical and spectroscopic results for pyrazolyl-d(3) and to spectroscopic results for pyrazolyl-h(3), for which no reliable simulations had been available.

Reducing power consumption is a major concern in mobile applications, since they are battery operated and require high performance. In this paper, a novel technique to reduce the power consumed by embedded SRAM memory is introduced. The proposed method is an on-chip circuit to measure the optimal data retention voltage (DRV) of the SRAM array. The implemented DRV computing circuit consists of a built-in-self-test (BIST) unit, a DC-DC converter and some control logic. The proposed technique can be used to accurately measure the DRV to ensure the SRAM operates at its minimum energy point. The circuit was developed in 90nm technology and simulated using HSPICE. Monte-Carlo simulation of 100k samples determined the DRV as 150mV whereas the proposed technique showed that the DRV of the SRAM under test could be lowered to 80mV which would result in significant power savings.