Minimum padding to satisfy short path constraints

This paper presents a model that can be easily used to resolve the energy hub operation problem. The proposed model considers the uncertainty in the input and output ports. The energy hub optimum operation problem needs to be resolved in order to supply several energy loads in combination at the minimum total energy cost. In this study, mixed-integer linear programming was applied to formulate this optimization problem. The power balance, energy storage, and converter limitations of the input and output ports were included as equality and inequality constraints. The total cost of an energy hub was determined by the price of energy carriers. Eventually, deterministic and stochastic versions of the proposed model were tested in a case study. In the test system, electricity, gas, and wind generation were used in the input port, and the output port contained the electrical and thermal load. The results demonstrated that a stochastic model based on different scenarios was more realistic than a deterministic model. However, the total operating cost of an energy hub decreased more in the stochastic model compared to the deterministic model.

In this paper, we purpose a novel approach to analyze exact cell loss probability of Shared Buffer ATM switch. In a N X N ATM switch whose input ports and output ports share one buffer, the number of arriving cells from input ports at one time slot is less than or equal to N. If these cells were destined to n output ports, no cells will be destined to the remaining N-n output ports. In the extremism, all arriving cells were destined to one output port, no cell will be destined to the other N-1 output ports. So, the arriving cells at each time slot from the input ports are destined to the output ports correlatively, but not independently. For this reason, the analyzing result on the assumption that all output cell queues are independent one another is larger than actual result. We complete our analysis by three steps. First, considering the case that there are cells arriving from input ports but not cells remove from output ports, we can get one-step state transition probability matrix P<SUB>a</SUB>; Second, considering the case that there are cells removing from output ports but not cells arrive from input ports, we can get one-step state transition probability matrix Ps; Third, considering arrival process and service process are independent, the accurate one-step state transition probability matrix P of cell's number in the buffer is derived, and then cell queue length steady probability distribution can be found. We can compute the accurate buffer capacity below certain cell loss probability. Computer simulation proves that the approach is efficient and exact.

The ternary T-gate can be used as a basic building block to construct both combinational and sequential circuits. Since the T-gate is one kind of tree-type universal logic module, any combinational circuit can be built up with modular logic arrays. For constructing ternary memory elements, however, the T-gate is required to be static hazard-free. A theoretical study is done on the necessary conditions for the practical realization of the static-hazard-free T-gate. On the basis of the result obtained, the static-hazard-free T-gate is realized using the ECL technique. The static-hazard-free T-gates obtained here can be used as building blocks to construct memory elements. Various memory elements such as D flip-flap-flop (FFF), D master-slave FFF, B master-slave FFF, and counting FFF is constructed easily. Using these memory elements, three different types of ternary counters can be designed and realized. They are an asynchronous signed ternary counter, a synchronous signed ternary counter, and a counter based on a shift register. Their design methods are discussed. These ternary counters are superior to the binary ones in that the up-down cotnting can easily be carried out by one input signal.

A formulation for design of continuous, hinge-free compliant mechanisms is developed and examined within a continuum structural topology optimization framework. The formulation makes use of two distinctly different sets of springs, the first of which are artificial springs of relatively large stiffness attached to the input and output ports of the mechanism model, and the second of which are springs attached only to the output port with smaller stiffnesses that represent the resistance of the workpiece as it is manipulated by the mechanism. The proposed formulation involves solving two nested optimization problems. In the inner problem the arrangement of a constrained amount of structural material is optimized to maximize the mechanism's mutual potential energy in response to a force loading at the input port while working against the stiff artificial springs on the input and output ports. As the relative stiffness of the artificial springs increases, the material continuity of the mechanism also increases to the point where de facto ‘hinge’ regions are eliminated. In the outer problem, the artificial springs are removed and one solves for an appropriate amount of structural material that yields the desired finite deformation compliance characteristics of the mechanism when working against the real workpiece resistance. Different aspects of the proposed formulation are demonstrated on a number of examples and discussed. Copyright © 2004 John Wiley & Sons, Ltd.

We describe a novel method for scheduling highspeed network switches. The targeted architecture is an input-buffered switch with a non-blocking switch fabric. The input buffers are organized as virtual output queues to avoid head-of-line blocking. The task of the scheduler is to decide when the input ports can forward packets from the virtual output queues to the corresponding output ports. Our Least Choice First (LCF) scheduling method selects the input and output ports to be matched by prioritizing the input ports according to the number of virtual output queues that contain packets: The fewer virtual output queues with packets, the higher- the scheduling priority, of the input port. This way the number- of switch connections and, with it, switch throughput is maximized. Fairness is provided through the addition of a round-robin algorithm. We present two alternative implementations: A central implementation intended for narrow, switches and a distributed implementation based on an iterative algorithm intended for wide switches. The simulation results show that the LCF scheduler outperforms other scheduling methods such as the parallel iterative matcher, iSLIP, and the wave front arbiter.

Two novel graphene-based nonreciprocal four-port splitters for the terahertz region are proposed. The input power is divided between two output ports, whereas the input port is isolated from the output ports due to the presence of the fourth port. The splitters consist of a circular graphene resonator and four graphene waveguides coupled to the resonator. These elements are placed on the two-layer dielectric substrate. The central part of the splitter is under a biasing DC magnetic field normal to the graphene layer. The surface plasmon-polariton wave in the input port excites the dipole resonance in the resonator. The splitters have the following parameters: the input power is divided between two output ports almost equally with -4.4 dB. The input port is isolated from two output ports by -15 dB. The bandwidth is 4.0% with a central frequency of 7.4THz. The biasing DC magnetic field is 0.8T, and the Fermi energy of graphene ϵF=0.15 eV. Changing the Fermi energy by electrostatic gating allows one to dynamically control the central frequency of the splitters.

Interconnection networks usually consist of a fabric of interconnected routers, which receive packets arriving at their input ports and forward them to appropriate output ports. Unfortunately, network packets moving through these routers are often delayed due to conflicting demand for resources, such as output ports or buffer space. Hence, routers typically employ arbiters that resolve conflicting resource demands to maximize the number of matches between packets waiting at input ports and free output ports. Efficient design and implementation of the algorithm running on these arbiters is critical to maximize network performance.This paper proposes a new arbitration algorithm called SPAA (Simple Pipelined Arbitration Algorithm), which is implemented in the Alpha 21364 processor's on-chip router pipeline. Simulation results show that SPAA significantly outperforms two earlier well-known arbitration algorithms: PIM (Parallel Iterative Matching) and WFA (Wave-Front Arbiter) implemented in the SGI Spider switch. SPAA outperforms PIM and WFA because SPAA exhibits matching capabilities similar to PIM and WFA under realistic conditions when many output ports are busy, incurs fewer clock cycles to perform the arbitration, and can be pipelined effectively. Additionally, we propose a new prioritization policy called the Rotary Rule, which prevents the network's adverse performance degradation from saturation at high network loads by prioritizing packets already in the network over new packets generated by caches or memory.

Interconnection networks usually consist of a fabric of interconnected routers, which receive packets arriving at their input ports and forward them to appropriate output ports. Unfortunately, network packets moving through these routers are often delayed due to conflicting demand for resources, such as output ports or buffer space. Hence, routers typically employ arbiters that resolve conflicting resource demands to maximize the number of matches between packets waiting at input ports and free output ports. Efficient design and implementation of the algorithm running on these arbiters is critical to maximize network performance.This paper proposes a new arbitration algorithm called SPAA (Simple Pipelined Arbitration Algorithm), which is implemented in the Alpha 21364 processor's on-chip router pipeline. Simulation results show that SPAA significantly outperforms two earlier well-known arbitration algorithms: PIM (Parallel Iterative Matching) and WFA (Wave-Front Arbiter) implemented in the SGI Spider switch. SPAA outperforms PIM and WFA because SPAA exhibits matching capabilities similar to PIM and WFA under realistic conditions when many output ports are busy, incurs fewer clock cycles to perform the arbitration, and can be pipelined effectively. Additionally, we propose a new prioritization policy called the Rotary Rule, which prevents the network's adverse performance degradation from saturation at high network loads by prioritizing packets already in the network over new packets generated by caches or memory.

An n-leaf pipelined balanced binary tree is used for arbitration of order and movement of data from n input ports to one output port. A novel arbitrate-and-move primitive circuit for every node of the tree, which is based on a concept of reduced synchrony that benefits from attractive features of both asynchronous and synchronous designs, is presented. The design objective of the pipelined binary tree is to provide a key building block in a high-throughput mesh-of-trees interconnection network for Explicit Multi Threading (XMT) architecture, a recently introduced parallel computation framework. The proposed reduced synchrony circuit was compared with asynchronous and synchronous designs of arbitrate-and-move primitives. Simulations with 0.18 /spl mu/m technology show that compared to an asynchronous design, the proposed reduced synchrony implementation achieves a higher throughput, up to 2 Giga-Requests per second on an 8-leaf binary tree. Our circuit also consumes less power than the synchronous design, and requires less silicon area than both the synchronous and asynchronous designs.

In this paper, we study the multiple voltage assignment (MVA) problem under timing constraints in floorplanning, which is generally an NP-hard problem. We will present an effective value-oriented branch-and-bound based algorithm to solve it optimally in a reasonable amount of time. A convex cost integer dual network flow approach is used to obtain a feasible upper bound solution, while a lower bound is obtained by a linear relaxation of a general formulation of the problem. We then adopt a value-oriented breadth-first branch-and-bound method with upper and lower bounds as described above to search for the optimal solution. Favorable results can be obtained in comparison with previous methods using a general linear programming solver. We integrate this algorithm into a multi-stage floorplanner. At the first stage, an initial floorplan is obtained by simulated annealing using the convex cost integer dual network flow approach as an evaluator. We then perform optimal voltage assignment to this initial floorplan. Finally, a post-processing step is done to modify the floorplan slightly to optimize the power network routing resource before invoking once more the optimal voltage assignment step at the end. Experimental results show that we can improve over the most updated work on this problem [7] by further reducing 6% of power consumption while maintaining the performance on other factors

Both long and short path delays are used to determine the valid clocking for various CMOS circuits such as single phase latching, asynchronous and wave pipelining. Therefore, accurate estimation of both long and short path delays is very crucial in the designing and testing of high speed CMOS circuits. Most of the previous approaches in detecting long and short sensitizable paths assume that the rising and falling of gate delays are either fixed or bounded. We propose several algorithms to compute the longest and shortest sensitizable path delays based on a data dependent delay model. A proposed algorithm which is based on a combination of modified static (topological) timing analysis and path sensitization techniques seems to offer the best performance. The results obtained have shown to be more accurate than the traditional path sensitization approach based on the bounded delay model. >

The paper describes a 4 × 4 laser diode optical gate switch made on an InGaAs/GaAs single quantum well GRIN-SCH wafer. The switches were made very compact (only 1.1 × 1.6 mm) by using a Y reflection type optical branching/combining circuit with wide-angle splitting. The light signal launched into an input port is transmitted to an output port through seven gate waveguides and six Y branching circuits. All of the paths between the input and output ports exhibit lossless switching operations when a current of 16 mA (average value) is injected into one gate. The excess loss of the Y branching circuit is estimated to be 0 dB for through coupling and 4 dB for crosscoupling. Good fabrication uniformity of the individual device elements (i.e. the gate waveguide and Y reflection type branching circuit) were confirmed in an area of 10 mm × 10 mm, which was one unit of the photolithography process used in the experiments. However, a significant difference in gain characteristics between the input–output paths in the 4 × 4 switches was observed. The disagreement between the uniformity of the individual elements and the scattering of the path gain characteristics can be explained by the zigzag propagation of the light beam eccentrically launched into the waveguides through the Y reflection type branching circuit.

The discovery of valley degrees of freedom in electronic and classical waves opened the field of valleytronics and offered the prospect for new devices based on valleys. However, the implementation of valley-based devices remains challenging in practice. Here, by taking advantage of the flexibility of phononic crystals in design and fabrication, the realizations of valley devices, or filters, valves, and diverters for acoustic waves are reported. All the devices are configured as the structures of input and output ports bridged by channels. The phononic crystals serving as ports allow the propagation of both valley polarizations, whereas the phononic crystals serving as channels, as they are narrow, only allow the propagation of single polarizations. For valley filters that achieve valley-polarized currents, the bridge channel is simply a straight single phononic crystal, but for valley valves that can turn off the valley-polarized currents, the channel consists of two parts, allowing the propagation of opposite valley polarizations. The valley diverters have one input port, and two output ports, and thus a branched channel, and the three parts in the channel allow the propagation of the same valley polarizations, so that the energy flow can be partitioned. The results may serve as a basis for developing advanced acoustic valley devices.

This paper introduces a three-port DC-DC converter (TPC) designed for enhanced voltage gain applications. The TPC features two input ports, including a bidirectional port for the charging and discharging of a battery. It incorporates a switched inductor to achieve higher voltage gains. The converter is capable of operating in four modes, one of which is a battery-alone mode. Compared to existing topologies, the proposed design significantly reduces input current ripple and ensures a common ground connection between the input and output ports. This configuration makes the TPC particularly suitable for renewable energy applications. The functionality and effectiveness of the proposed converter are validated through an experimental prototype with a power of around <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">400 W</i> . The experiments verified the converter’s dynamic performance during load step changes and mode transitions.

The data path and memory elements are integral hardware components to evaluate the performance of a complex ASIC low power architecture. In this study, a FinFET model was evaluated via 7 nm FinFET process using ASAP PDK and applied to 6T SRAM cells and 32-bit ALU architecture. Devices of 0.207 V threshold were biased at 0.7V supply voltage. The clock router was properly modeled with accurate values of resistances and capacitances for the metal layers. The noise glitch and cross talk within the parallel running interconnects and the driving loads were incorporated in the model. A command set clock uncertainty is also integrated into the model to incorporate the clock jitter and clock skew effects. The architecture was optimized for worst case scenario with typical RC corners. The Non-Linear Delay Model (NLDM) was incorporated for the cell synthesis where a delay that is based on the input transition and output load capacitance was incorporated for better quality of results (QoR). The low power architecture was evaluated for worst case scenario considering typical-typical (TT) corners. A maximum effective device current of 18.26µA with subthreshold slope of 60mV/decade were estimated and considered in the system evaluation. The output ports were loaded with a typical 2fF capacitance. At 1 GHz operation, the internal power, switching power, and leakage power are reported to be 0.2705 mW, 0.7599 mW, and 0.00743 mW, respectively.