Mitigate the Side Channel Attack Using Random Generation with Reconfigurable Architecture

Random chunks generation attack is a more sophisticated form of side channel attack in cross-user chunk level deduplication, in which the target chunks are checked together with randomly generated non-duplicate ones. When the number of required chunks or linear combinations equals to that of the randomly generated chunks, this issue prevents existing schemes from achieving obfuscation in the response, thereby compromising the existence privacy of the target chunks. Moreover, this vulnerability becomes even more pronounced under the hybrid attack, in which a portion of the target chunks is replaced by public ones. To address both kinds of attacks in a lightweight way, we propose a hotness strategy based secure cross-user deduplication scheme (HSDS) for cloud storage. Specifically, the cloud service provider (CSP) records the feature hotness and chunk hotness of duplicate chunks before defining specific chunks to be non-duplicate in response generation. Both the security analysis and experimental results show that the probability to expose the existence of sensitive chunks of the proposed scheme is negligible, which is effective in resisting the random chunks generation attack and its hybrid form in a lightweight way.

In this paper the experimental validation of a novel, modified double scroll chaotic attractor circuit, employed as a true random binary generator (TRBG) is presented. The double scroll attractor is modeled on Chua's circuit constituted as independent chaotic oscillator using passive only nonlinear device for nonlinear operation leading to chaotic behavior. The output from the chaotic circuit which is a correlated binary sequence is scrambled with a pseudo random binary sequence generator (PRBSG) topology to yield a true random binary source for key stream generation. The modified chaotic circuit has been first modeled in PSpice software. The randomness attributes of the modified generator, obtained from both the PSpice model and hardware implementation, using the PRBSG de-correlator were successfully tested by the well known NIST Test Suite and Diehard Test Set for statistical validation. Output binary streams from the proposed modified generator were examined for randomness using both Test Suites with all tests successfully passed for both PSpice model and experimental chaotic circuit generator. A physical TRBG has been constructed on the basis of the proposed PRBSG modification with all statistical tests successfully passed confirming theoretical expectations. (6 pages)

In most of quantum key distribution schemes, real random number generators are required on both sides for preparation and measurement bases choice. In this paper, via entangled photon pairs, we present a side channel passive quantum key distribution scheme, in which random number generator is unneeded on the receiver side. On the sender Alice side, along with massive of signal photons, small amount of uninformative photons are randomly sent to her partner Bob for eavesdropper-presence testing and error estimation. While on the other side channel, without using random number generator Bob do not actively measure the income signals randomly in two non-orthogonal bases. Instead, he just passively register photon click events, in two settled symmetric (i.e.X) bases, and the raw key(click events) is the probable outcomes of a special quantum measurement module constructed by Alice and Bob. Further, security analysis and formulas of security bounds for this scheme is also investigated under reasonable assumptions. Our work shows that the uninformative state employed in this paper is powerful to fight against eavesdropper Eve.

In this paper we consider a side-channel attack on a chaos-based random number generator (RNG) based on power consumption analysis. The aim of this attack is to verify if it is possible to retrieve information regarding the internal state of the chaotic system used to generate the random bits. In fact, one of the most common arguments against this kind of RNGs is that, due to the deterministic nature of the chaotic circuit on which they rely, the system cannot be truly unpredictable. Here we analyze the power consumption profile of a chaos-based RNG prototype we designed in 0.35 mum CMOS technology, showing that for the proposed circuit the internal state (and therefore the future evolution) of the system cannot be determined with a side-channel attack based on a power analysis. This property makes the proposed RNG perfectly suitable for high-security cryptographic applications.

The cryptographic security provided by various techniques of random number generator (RNG) construction is one of the developing research areas today. Among various types of RNG, the true random bit generator (TRBG) can be considered as the most unpredictable and most secure because its randomness seed is generated from chaotic sources. This paper proposes a design of TRBG model based on double-scroll attractors circuits with GST memristor. After implementation and simulation of the chaotic circuit with GST memristor emulator, the chaotic behavior of the output voltage and inductor current were received. Moreover, their dependence on the input voltage revealed the close to double-scroll form. The randomness generated from the proposed circuit was tested by analysis of the Fast Fourier Transform (FFT) and Lyapunov exponents of the output voltage.

Side channel analysis(SCA) focuses on attacking cryptographic algorithm implementations by collecting leaked information and analyzing the correlation between the leaked and key information in the cryptographic system. Currently, SCA is the main threat to cryptographic implementations, with DPA (differential power analysis) and DFA (differential fault analysis) being two of the most threatening types of SCA. However, the existing countermeasures against DPA and DFA have shortcomings and can hardly protect cipher designs perfectly. Based on a comprehensive analysis of DPA and DFA, this paper proposes a new idea of using an evolutionary cipher (EVOC) against DPAs based on the model proposed by Kocher, and several different new types of DFAs. In fact, an EVOC is a kind of dynamic cipher designing method. Moreover, combined with intelligent searching algorithms and cryptography design policies, EVOCs utilize the dynamic and unpredictable properties of TRNG (a truly random number generator) to ensure cipher design at a high level of security. Therefore, with an EVOC we could design cryptography algorithms with high security to resist mathematical analysis as well as DPAs and DFAs. This paper analyzes and proves the security, efficiency, cost, and original features of EVOCs against DPA and DFA both theoretically and experimentally. Compared with existing countermeasures against SCAs, EVOCs use dynamic non-linear operations to destroy the bases of DPA and DFA. At the algorithm level, EVOCs are more efficient than other resistance methods. Based on the theory and experiments, this paper proposes certain modifications to the EVOC in the AES (advanced encryption standard) algorithm, which can be referenced by other dynamic designs of cryptographic algorithms.

Masking is the main countermeasure against side-channel attacks due to its sound formal proof of security and the scalability of its protection parameters. However, effective masking increases the implementation complexity by requiring additional silicon area, random number generators and higher latency. Thus, reducing the masking implementation costs while conserving its robustness under side-channel attacks is a relevant branch of research in hardware security applications. Relying on the two-phase bundled-data protocol, this work presents a low-latency masking implementation with arbitrary protection order. In particular, we base our approach on the click elements to control the handshake logic, allowing us to implement asynchronous circuits using conventional synthesis tools. In this manner, we are able to obtain an effective single-cycle and protected implementation of the AES S-box requiring smaller silicon area and potentially lower power consumption compared to the state-of-the-art. Additionally, we detail the asynchronous design methodology that can be applied in different scenarios to improve the latency of secure hardware designs. Finally, we assess leakages to evaluate the robustness of our approach against side-channel attacks.

Since side channel analysis was introduced as a method to recover secret information from an otherwise secure cryptosystem, many countermeasures have been proposed to prevent leakage from secure devices. Among these countermeasures is side channel atomicity that makes operations indistinguishable using side channel analysis. In this paper, we present practical results of an attack on RSA signature generation, protected in this manner, based on the expected difference in Hamming weight between the result of a multiplication and a squaring operation. This work presents the first attack that we are aware of where template analysis can be used without requiring an open device to characterize an implementation of a given cryptographic algorithm. Moreover, an attacker does not need to know the plaintexts being operated on and, therefore, blinding and padding countermeasures applied to the plaintext do not hinder the attack in anyway.

Computers are complicated, and the security of modern software often depends on programmers anticipating and mitigating a dizzying assortment of vulnerability classes. Both researchers and adversaries continue to add additional complications based on hardware behavior to this mix, such as data-dependant power consumption, fault injection, cache timing attacks and transient execution - adding new attack surface which needs to be taken into account when building secure systems. In this dissertation, we look beyond the traditional attack surface, and find that many mitigations - across a variety of layers, from hardware to software - are compromised by faulty assumptions about the actual behavior of hardware. We begin close to the hardware, discovering that the relationship between two different forms of hardware attack - Fault Injection and Side-Channel Analysis - is so strong that we can find ways to apply power side-channel attack techniques directly to the results of voltage fault injection campaigns, without the need for an attacker to obtain power measurements. Next, we move to microarchitectural attacks - which rely on hardware behavior, but can be performed by software. By combining transient execution with unexpected - and unintended - CPU pipeline behavior, we show that the scope of software side-channel attacks can be expanded far beyond previous work, allowing both in-flight and 'stale' data to be stolen from the pipeline by an attacker, bypassing software mitigations by ignoring security domains entirely. Such attacks can be mitigated by isolating workloads on different cores - which do not share a pipeline. Unfortunately, we find that even this level of isolation can fail to prevent attackers from being able to leak critical data using side-channel attacks - such as random numbers used when generating cryptographic keys. Hence, these attacks must be mitigated in hardware. Finally, we investigate defenses against transient execution attacks such as Spectre which depend only on well-understood hardware behavior, but require software mitigations. We show that we can build efficient and practical software-based defenses which not only mitigate many Spectre attacks, but even harden software against architectural information leaks.

Since the introduction of the first side-channel analyses in academia about 15 years ago, several physical attacks have been presented that exploit side-channel leakages to break implementations of cryptographic algorithms. This article deals with the same physical property of electronic devices, but focuses on the art of tailoring it for constructive uses. More precisely, two scenarios, i.e., hardware Trojans and IP watermarking, are illustrated in which the designer of an electronic circuit can add functionality by considering side channels as part of the available design space. Both applications use the same concept, i.e., deliberately leaking a secret through a side channel while keeping the introduced side channel hidden from adversaries and attackers. This article provides a broad overview of the existing works for both applications and should serve as a comprehensible introduction to the underlying field of research. This includes many subtle details that have not been discussed in literature yet, including existing shortcomings and possible improvements to the existing works. The solutions summarized in this article provide general guidelines for theorists and practitioners to use side channels constructively to achieve designs that are robust against detection and removal. Furthermore, we present an entirely new design of a Trojan side-channel. This architecture demonstrates the potential of a Trojan side-channel that is neatly tailored to the targeted implementation. The new design removes all non-invasive starting points a third party could use to analyze or get access to the secret-channel.

The building blocks of several block ciphers involve arithmetic operations, bitwise operations and non-linear functions given as SBoxes. In the context of implementations secure against Side Channel Analysis, these operations shall not leak information on secret data. To this end, masking is a widely used protection technique. Propagating the masks through non-linear functions is a necessary task to achieve a sound and secure masked implementation. This paper describes an efficient method to securely access N SBoxes when the N inputs are encoded as a single word arithmetically masked. This problematic arises for instance in a secure implementation of the standard block ciphers GOST or SEED. A method using state of the art algorithms would be to first perform an arithmetic to boolean mask conversion before independently accessing the N SBoxes. Compared to this method, the algorithm proposed in this paper needs less code, less random generation and no extra memory. This makes our algorithm particularly suitable for very constrained devices. As a proof of concept, we compare an implementation in 8051 assembly language of our algorithm to the existing solutions.

Present day's data security plays a vital role in digital human life. Data is a valuable asset to any organization and hence its security from external attacks is very important. Information security is not only an important aspect but essential, to secure data from unapproved access. Data encryption, decryption and key management are the key factors in data protection. It is very important to have the right data security solution to meet the challenging threats. Cryptosystem implementation and random number generators are crucial for Cryptosystem applications such as security applications, space applications, military applications and smart cards et al. In this paper, we present the implementation of hybrid cryptosystem based on the True Random number Generator, pseudo Random number Generator and whitening the data by using the ASIC design flow.

Masking schemes represent a well-researched and successful option to follow when considering side-channel countermeasures. Still, such measures increase the implementation cost in terms of power consumption, clock cycles, and random numbers generation. In fact, the higher the order of protection against side-channel adversaries, the higher the implementation cost of countermeasures. S-boxes represent the most vulnerable part in an implementation when considering side-channel adversary. In this paper, we investigate how to generate S-boxes that have improved resilience against varying orders of side-channel attacks while having minimal implementation costs. We examine whether S-boxes generated against a certain order of attack also represent a good solution when considering different order of attacks. We demonstrate that we successfully generated S-boxes resilient against a certain physical attack order but the improvements are small. As a result, S-boxes that are resilient against first order attacks stay resilient against higher-order attacks, which saves computational power during the design of higher-order side-channel attacks resilient S-boxes.

There is a theoretically strong relationship between chaos and cryptology. In practice, one of the most successful applications of this relationship is chaos-based s-box structures. However, the performance metrics of chaos-based s-box designs are worse compared to those for s-box structure based on algebraic techniques used in modern encryption algorithms, such as the AES algorithm. What is the reason for using chaos-based s-box structures, even though they have worse cryptographic characteristics? Researchers claim that they may be an alternative defense against implementation attacks, especially side-channel analyses. However, no studies have supported or refuted this claim so far. In this paper, side-channel analyses have been performed for two different chaos-based s-box structures. These two s-box structures have been selected for having with the best and worst performance measurements for s-box structures previously proposed in the literature. The results were compared with the AES s-box structure. Analysis of the results showed that chaos-based s-box structures are more resistant against side-channel attacks. Therefore, chaos-based designs may be an alternative defense against implementation attacks, as alleged. However, both algebraic and chaos-based s-box designs have been observed to be insecure if the attacker has more than 30 plaintexts in the side channel analyses. These results show that implementation analysis studies are required in the chaos-based cryptology literature.

Cross-user deduplication is an effective technique means to eliminate redundant uploading in using cloud storage by returning a specific response to indicate existence of the data in request. However, the deterministic response actually provides a side channel to attackers, which could be utilized to steal existence privacy of the target data in cloud storage. Because of the difficulty to achieve complete obfuscation in response for chunk level deduplication, such kind of attack still cannot be well resisted, let alone random chunks generation attack, a more sophisticated form to assist statistical attacks. Even though dirty chunks processing is able to resist such attacks under normal circumstances, a lot of communication overhead is introduced inevitably. To deal with these challenges, we propose a marking based obfuscation strategy in cross-user deduplication for cloud storage, which takes the lead to well improve security in cross-user deduplication under side channel attack as well as random chunks generation attack. Specifically, we first calculate the number of chunks to be marked to cover at least one duplicate chunk with great probability. Then perform marking strategy to the certain number of randomly chosen chunks, to consider them as inexistent before generating a response regardless of their real existence. To achieve light weight dirty chunks processing with security guaranteed, as long as at least a dirty chunk is found to be involved in the request, once more marking is introduced to achieve another obfuscation. The experimental results show that, the proposed scheme is lightweight in achieving security comparing with the state-of-the art.