Modeling OPC complexity for design for manufacturability

With continued aggressive process scaling in the subwavelength lithographic regime, resolution enhancement techniques (RET) such as optical proximity correction (OPC) are an integral part of the design to mask flow. OPC adds complex features to the layout, resulting in mask data volume explosion and increased mask costs. Traditionally the mask flow has suffered from a lack of design information, such that all features (whether critical or non-critical) are treated alike by RET insertion. Gupta et al. (2003) proposes to exploit design information (timing slacks) to reduce OPC data volume, but has a number of impractical aspects. In this paper, we propose an implementable flow that drives model-based OPC explicitly by timing constraints, with the objective of reducing mask data volume and OPC runtime. We apply a mathematical programming based slack budgeting algorithm to determine edge placement error (EPE) tolerance budgets for all polysilicon gate geometries. These tolerances are then enforced by a commercial OPC tool to achieve up to 24% MEBES data volume and 41% OPC runtime reductions on a suite of six testcases implemented in Artisan TSMC 0.13 /spl mu/m libraries.

As the process technology advances to the nanometer nodes, Optical Proximity Correction (OPC) is the most popular Resolution-Enhancement Technique (RET) in industry for subwavelength lithography, and the inter-level dielectric (ILD) thickness variation caused by the planarization step of the Chemical-Mechanical Polishing (CMP) process also plays a key role for interconnect yield. Considering the OPC and CMP effects simultaneously during the routing stage can significantly alleviate the width and thickness variations (and thus the whole 3D geometry variations) of post-layout RET and CMP operations. In this paper, we first present an efficient, yet sufficiently accurate closed-form formula for printed width computation and dummy-insertion-aware routing cost derivation. The formula provides a cost modeling for post-layout OPC and CMP optimization during routing. Incorporating the OPC and CMP costs, the router can be guided to optimize the effects of layout correction and planarization. Compared with the state-of-the-art OPC-friendly router, QL-MGR (which does not consider CMP), the experimental results show that our approach can achieve respective 19% and 6% reductions in the maximum and average layout distortions. Compared with the state-of-the-art CMP-aware router, TTR (which does not consider OPC), the experimental results show that our approach can achieve respective 19% and 25% reductions in the peak-to-peak thickness and thickness variance. These results indicate that our simultaneous OPC- and CMP-aware router contributes a significant improvement for layout integrity.

The 22nm node will be patterned with very challenging Resolution Enhancement Techniques (RETs) such as double exposure or double patterning. Even with those extreme RETs, the k1 factor is expected to be less than 0.3. There is some concern in the industry that traditional edge-based simulate-then-move Optical Proximity Correction (OPC) may not be up to the challenges expected at the 22nm node. Previous work presented the advantages of a so-called inverse OPC approach when coupled with extreme RETs or illumination schemes. The smooth mask contours resulting from inverse corrections were shown not to be limited by topological identity, feedback locality, or fragment conformity. In short, inverse OPC can produce practically unconstrained and often non-intuitive mask shapes. The authors will expand this comparison between traditional and inverse OPC to include likely 22nm RETs such as double dipole lithography and double patterning, comparing dimensional control through process window for each OPC method. The impact of mask simplification of the inverse OPC shapes into shapes which can be reliably manufactured will also be explored.

Design weak points, or “hotspots” remain a leading issue in advanced lithography. These often lead to unexpected critical dimension (CD) behavior, degradation of process window and ultimately impact wafer yield. Industry technology development focus on hotspot detection has included full chip lithography simulation and machine learning-based hotspot analysis. Most recently, the machine learning approach is gaining attention because it is faster and more practical than lithography simulation-based hotspot detection. The machine learning case is a feedback approach based on previous known design hotspots. Conversely, the simulation method has the benefit of proactively detecting hotspots in a new design regardless of historical data. However, full chip simulation requires resources in calculating time, computing power and additional time-to-market that render it impractical in some scenarios. As design rules shrink, advanced mask designs have significantly increased in complexity due to Resolution Enhancement Techniques (RET) such as Source Mask Optimization (SMO), advanced Optical Proximity Correction (OPC) and high transmission attenuating mask films. This complicates hotspot detection by existing OPC verification tools or rigorous lithographic simulation with wafer resist model. These resultant complex mask geometries make OPC optimization and hotspot detection using post design very difficult. In this paper, we will demonstrate the limitation of traditional hotspot detection technology. Typical OPC tools use simple techniques such as single Gaussian approximations on the design, such as corner rounding, to take the mask process impact to the geometry into account. We will introduce a practical lithography hotspot identification method using mask process model. Mask model-based hotspot detection will be used to precisely identify lithography hotspots and will provide the information needed to improve hotspots’ lithographic performance.

Sub-Resolution Assist Feature (SRAF) insertion is one of the most important Resolution Enhancement Techniques (RET) for the 65 nm, 45 nm nodes and beyond. In this paper, we are proposing a novel approach for the optimum placement of SRAF structures using state of the art Calibre RET flow. In this approach, the optimal SRAF shapes are achieved simultaneously during the Optical Proximity Correction (OPC) stage. The main features and the SRAFs are optimized to account for their edge placement and process window metrics respectively. The resulting mask shapes deliver some of the properties that can be obtained using the Inverse Lithography Techniques (ILT), such as excellent Process Window Performance, while there is almost no impact on the runtime. The implemented model-based optimization flow remains compatible with the current OPC production flows.

As technology advances with feature size shrinking for the state-of-the-art integrated circuit (IC) fabrication, the degree of reduction in critical dimension (CD) features on a photomask shrinks at a faster pace, thanks to the ever aggressive optical proximity correction (OPC) design. In addition to stringent CD requirement, defect control has also become one of the most difficult challenges for advanced photomask manufacturing as a result of reduction in printable defect size. Therefore, keeping a photomask etching chamber at an optimal condition becomes very critical for controlling in both defectivity and CD fidelity. In the present study, analyses on optical emission spectrum (OES) collected in an Applied Materials' Tetra^TM chrome etch module have been performed to understand (1) the impact of Cr etching on the chamber condition, and (2) the effectiveness of in-situ chamber dry clean for chamber condition control and potential particle reduction. Results showed that, with the right selection of chamber materials (to be compatible with process chemistry and etching condition), the main impact of Cr etching on chamber condition and particle performance is from resist etch-by-products. Various plasma dry clean chemistries have been explored to address the effectiveness for the removal of such etch-by-products. As a result, an in-situ chamber clean (ICC) procedure is developed and has been validated to be production-worthy for desired particle control and chamber stability control.

Optical proximity correction (OPC) methods are resolution enhancement techniques (RET) used extensively in the semiconductor industry to improve the resolution and pattern fidelity of optical lithography. Recently, a set of generalized gradient-based OPC optimization methods have been developed to solve for the inverse lithography problem under coherent illumination. Most practical lithography systems, however, operate under partially coherent illumination due to non-zero width sources and off-axis illumination from spatially extended sources. OPC methods derived under the coherent illumination assumption fail to account for the nonlinearities of partially coherent illumination and thus perform poorly in the latter scenario. This paper focuses on developing gradient-based binary mask optimization methods which account for the inherent nonlinearities of partially coherent systems. Two nonlinear models are used in the optimization. The first relies on a Fourier representation of the nonlinear model which approximates the partially coherent system as a sum of coherent systems. The second model is based on an average coherent approximation which is computationally faster. In order to influence the solution patterns to have more desirable manufacturability properties, wavelet regularization is added to the optimization framework. The advantages and limitations of both models in the inverse lithography problem are discussed and several illustrative simulations are presented.

As the feature size of advanced integrated circuits keeps shrinking, resolution enhancement technique (RET) is utilized to improve the printability in the lithography process. Optical proximity correction (OPC) is one of the most widely used RETs aiming at compensating the mask to generate a more precise wafer image. In this paper, we put forward a level-set based OPC with high mask optimization quality and fast convergence. In order to suppress the disturbance of the condition fluctuation in lithography process, we propose a new process window-aware cost function. Then, a novel momentum-based evolution technique is adopted, which demonstrates substantial improvement. Moreover, graphics processing unit (GPU) is leveraged for accelerating the proposed algorithm. Experimental results on ICCAD 2013 benchmarks show that our algorithm outperforms all previous OPC algorithms in terms of both solution quality and runtime overhead.

Due to the sub-wavelength lithography, manufacturing sub-90 nm feature sizes require intensive use of resolution-enhancement techniques, among which optical proximity correction (OPC) is the most popular technique in industry. Considering the OPC effects during routing can significantly alleviate the cost of post-layout OPC operations. In this paper, we present an efficient, accurate, and economical analytical formula for intensity computation and develop the first modeling of post-layout OPC based on a quasi- inverse lithography technique. Extensive simulations with SPLAT, the golden lithography simulator in academia and industry, show that our intensity formula has high fidelity. Incorporating the OPC costs computed by the quasi-inverse lithography technique for our post-layout OPC modeling into a router, the router can be guided to maximize the effects of the correction. Compared with a rule- based OPC method, the experimental results show that our approach can achieve 14% and 16% reductions in the maximum and average layout distortions, respectively.

With the dramatically increase of design complexity and the advance of semiconductor technology nodes, huge difficulties appear during design for manufacturability with existing lithography solutions. Sub-resolution assist feature (SRAF) insertion and optical proximity correction (OPC) are both inevitable resolution enhancement techniques (RET) to maximize process window and ensure feature printability. Conventional model-based SRAF insertion and OPC methods are widely applied in industrial application but suffer from the extremely long runtime due to iterative optimization process. In this paper, we propose the first work developing a deep learning framework to simultaneously perform SRAF insertion and edge-based OPC. In addition, to make the optimized masks more reliable and convincing for industrial application, we employ a commercial lithography simulation tool to consider the quality of wafer image with various lithographic metrics. The effectiveness and efficiency of the proposed framework are demonstrated in experimental results, which also show the success of machine learning-based lithography optimization techniques for the current complex and large-scale circuit layouts.

As an important resolution enhancement technique (RET), alternating aperture phase shift masks (AAPSM) has been widely adopted in 90 nm technology node and beyond. Mask topographical effect due to the 3D nature of the shifter features is becoming an increasingly important factor in lithography modeling. Rigorous 3D modeling of PSM is very computationally demanding thus impractical for full chip optical proximity correction (OPC). Here we introduce an alternative approach employing boundary layers to effectively approximate the 3D mask effect. We will present the model calibration versus real wafer data using the boundary layers and the corresponding OPC correction flow.

The fast pattern shrinkage of DRAM has driven the lithography technology into the low k1 regime for sub-60 nm technology node. There are a lot of resolution enhancement techniques (RETs) e.g. OPC (Optical Proximity Correction), SB (Scattering Bar), SRAF (Sub-Resolution Assist Features) and DDL (Double Dipole Lithography) and Alternating PSM to enable the low k1 lithography [4]. However, among the RETs, the alternating PSM technique is a high cost solution because double exposure is needed to avoid phase conflict error. Therefore, the implementation of alternating PSM with single exposure for gate conductor layer is the main purpose of this study. Many kinds of pattern and phase designs in the main cell and periphery were investigated.

With the technology node entering 45nm and below and the delay of the EUV lithography, the resolution enhancement techniques (RET) has been considered indispensable to extend the life time of conventional 193nm lithography. Traditional RETs, for example, optical proximity correction (OPC), phase-shifting mask (PSM), inverse lithography technique (ILT) and so on, use a fixed source thus limiting the degrees of freedom during the mask pattern optimization. To overcome the restriction, recently, source and mask co-optimization (SMO) has been proposed as a strong contender in RET. However, SMO is very computationally intensive. To mitigate the issue, we adopt a method which has demonstrated in good effectivity and efficiency in illumination source optimization. Based on the gray-level pixel based source representation, the gradient of the cost function is calculated to guide optimization to improve the wafer image fidelity and depth of focus (DOF). Moreover, the similar method has been used in mask optimization to form a complete SMO algorithm. The SMO algorithm is demonstrated using two mask patterns with critical dimension (CD) of 45nm, including a periodic array of contact holes and a tri-bar pattern. Both the results showed high image quality have been achieved using our SMO algorithm.

As design rules continue to shrink towards 4x nm, there are increase usage of aggressive Optical Proximity Correction (OPC) in reticle manufacturing. One of the most challenging aggressive OPCs is Sub Resolution Assist Feature (SRAF) such as scattering and anti-scattering bars typically used to overlap isolated and dense feature process windows. These SRAF features are sub-resolution in that these features intentionally do not resolve on the printed wafer. Many reticle manufacturers struggle to write these SRAFs with consistent edge quality even the most advanced E-Beam writers and processes due to resolution limitations. Consequently, this inconsistent writing gives reticle inspection challenges. Large numbers of such nuisance defects can dominate the inspection and impose an extraordinarily high burden on the operator reviewing these defects. One method to work around inconsistent assist feature edge quality or line-end shortening is to adjust the mask inspection system so that there is a substantial sensitivity decrease in order to achieve good inspectability, which then compromises the sensitivity for the defects on main geometries. Modern defect inspection tools offer multiple modes of operation that can be effectively applied to optimize defect sensitivity in the presence of SRAF feature variability. This paper presents the results of an evaluation of advance inspection methods and modes such as die to database selective thinline desense, transmitted & reflected light inspections, review system and die to die selective desense to increase inspectability and usable sensitivity using challenging production and R&D masks. Key learnings are discussed.

As minimum feature sizes continue to shrink, patterned features have become significantly smaller than the wavelength of light used in optical lithography. As a result, the requirement for dimensional variation control, especially in critical dimension (CD) 3σ, has become more stringent. To meet these requirements, resolution enhancement techniques (RET) such as optical proximity correction (OPC) and phase shift mask (PSM) technology are applied. These approaches result in a substantial increase in mask costs and make the cost of ownership (COO) a key parameter in the comparison of lithography technologies. No concept of function is injected into the mask flow; that is, current OPC techniques are oblivious to the design intent. The entire layout is corrected uniformly with the same effort. We propose a novel minimum cost of correction (MinCorr) methodology to determine the level of correction for each layout feature such that prescribed parametric yield is attained. We highlight potential solutions to the MinCorr problem and give a simple mapping to traditional performance optimization. We conclude with experimental results showing the RET costs that can be saved while attaining a desired level of parametric yield.