Modelling a 2-D inverse fast cosine transform algorithm on a multistage network

Interconnection network front-end controller combining to reduce hot spots effects

In large-scale supercomputers thousands of processors are connected together to their respective memory modules which are controlled by several control units connected in parallel. Large data streams have to be communicated between these processors and memories through interconnection networks. Multistage interconnection network (MIN) is an efficient way to provide these communications at a very reasonable cost. For such large systems MIN employed should be highly reliable and fast to meet the desired specifications of these high speed switch fabrics. In this paper two new architectures of MIN are proposed which are named as fault-tolerant Gamma-Minus (FTGM-1 & FTGM-2) networks. These proposed architectures are multipath MIN with totally disjoint paths and are highly reliable and fault tolerant. The routing algorithm proposed for these structures is simple distance tag routing with non-backtracking which overcomes rerouting overheads and hence improve communication delays. The proposed MIN ensures multiple fault tolerance at each stage including input and output stage with minimal horizontal distance between source node to destination node. For validating the results, a comparison has been presented between existing MINs with these proposed designs. The proposed MINs outperform the existing MIN in terms of reliability, fault tolerance and up to some extent cost as well.

This paper studies the non‐blocking conditions of a genericN × Nmultistage interconnection network, such as an omega network or ann‐cube network, in which only one path connects any inlet to each outlet and different I/O paths can share interstage links. It is widely known that any of these networks is non‐blocking for a compact and monotone pattern ofk≤NI/O paths. Recently it has become very important to show the network non‐blocking property for permutation sets, wider than the compact and monotone, which are usually encountered in broadband ATM networks. By using a new approach based on the concept of distance between I/O paths, we show here that these networks are non‐blocking for a set of I/O paths obtained by shifting cyclically the inlets of a compact and monotone pattern of I/O paths by an arbitrary number of steps.

A fault tolerant multistage interconnection network with partly duplicated switches

A ‘fibre‐switch block’ is a switch with delay lines that feedback from some outputs to inputs. In every unit time, it receives and transmits a packet concurrently. A ‘fibre memory’ means a multi‐block serial connection. Its performance of time‐multiplexed operation is often said to ‘emulate’ a multistage interconnection network. This study formulates this concept of emulation. The formalised concept is useful in the design and validation of various switching functionalities, including timeslot interchanging, sorting, merging and concentration. For illustration, ‘banyan‐type networks’, ‘Clos network’ and several familiar multi‐stage sorting networks are all efficiently emulated.

Multistage interconnection networks are used as a medium for interconnecting processors and memories in multiprocessor systems. Multistage interconnection networks are an effective substitute for crossbar switches, used in telephone network systems and parallel computers, due to their low cost, better performance and easy maintainability. In this paper, we propose new fault-tolerant hybrid multistage interconnection networks obtained from shuffle exchange gamma interconnection network (SEGIN) and logical neighborhood network named as shuffle exchange gamma logical neighborhood interconnection network (SEGLNIN). We evaluated the performance of SEGLNIN in terms of disjoint paths, reliability and hardware cost and compared it with some well-known MINs like shuffle exchange network (SEN), shuffle exchange network with one extra stage (SEN +) and shuffle exchange network with two extra stages (SEN + 2), SEGIN-1, and SEGIN-2. The results illustrate that the performance of the proposed SEGLNIN is better than that of the compared networks in terms of reliability and disjoint paths.

Problem statement: A class of dynamic interconnection networks is Multistage Interconnection Networks (MINs) that connects input devices to output devices through a number of switch stages. MINs have assumed importance in recent years; because of their cost-effectiveness. Optical MINs are one type of MINs that have large transmission capacity in the communication networks. There is a major problem in Optical MIN that is crosstalk, which is caused by coupling two signals within a switching element. Approach: To avoid crosstalk in Optical MINs many algorithms have been proposed by many researchers that we review applying five routing algorithms and scheduling them in the Optical MINs. Results: The comparative results of routing algorithms show affective of avoiding crosstalk in number of passes and execution time for different algorithm. Conclusion: The challenge between these routing algorithms is thoroughly investigated, by applying them on Optical MIN and showing which algorithm has better performance to avoid crosstalk.

A multistage interconnection network (MIN) for multiprocessor systems is proposed. The proposed MIN, called the B-network, uses backward links to provide backward paths for the requests blocked at switches or memory due to contentions. The gamma network is known to contain a cube network (specifically, the inverse omega network) as a substructure. The B-network is obtained from the gamma network by preserving the cube structure but reversing the direction of all other links. These backward links are used as alternate paths for requests blocked due to path or memory contentions. The B-network can be controlled by the simple destination tag control algorithm; packets navigating through the B-network, using both regular forward links and backward links, can reach their destinations under the destination tag control. The performance of the B-network is analyzed under the uniform traffic model and compared to various networks of interest. It is shown that the B-network surpasses the performance of the gamma network, the crossbar switch, and single-buffered MINs based on (2*2) switches, while having the same hardware complexity as the gamma network.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-performance supercomputers generally comprise millions of CPUs in which interconnection networks play an important role to achieve high performance. New design paradigms of dynamic on-chip interconnection network involve a) topology b) synthesis, modeling and evaluation c) quality of service, fault tolerance and reliability d) routing procedures. To construct a dynamic highly fault tolerant interconnection networks requires more disjoint paths from each source-destination node pair at each stage and dynamic rerouting capability to use the various available paths effectively. Fast routing and rerouting strategy is needed to provide reliable performance on switch/link failures. This paper proposes two new architecture designs of fault tolerant interconnection networks named as reliable interconnection networks (RIN-1 and RIN-2). The proposed layouts are multipath multi-stage interconnection networks providing four disjoint paths for all the source-destination node pairs with dynamic rerouting capability. The designs can withstand switch failures in all the stages (including input and output stages) and provide more reliability. Reliability analysis of various MIN architectures is evaluated. On comparing the results with some existing MINs it is evident that the proposed designs provides higher reliability values and fault tolerance.

Vertical stacking is a novel scheme in creating nonblocking multistage interconnection networks (MINs). Available results indicate that under the crosstalk-free constraint, the hardware cost is high for a strictly nonblocking optical MIN based on the scheme. Packing strategy is a commonly used routing strategy for reducing network hardware. In this paper, we look into the nonblocking conditions for crosstalk-free optical MINs under packing strategy. It is shown that packing strategy is very efficient in reducing the hardware cost of a nonblocking optical MIN under the crosstalk-free constraint. The results in the paper will be useful in designing optical MINs.

Two new construction methods for multistage interconnection networks (MINs) are proposed. These methods provide low overhead in enlarging the size of MIN scheme and they have the same features as those of MIN schemes by typically designed method. The first proposed method proves that, in enlarging the size of MIN scheme, the full access interconnection property and the self-routing ability are also available in the enlarged scheme and the hardware and reconstruction overhead is low. However, the requests to be accepted by the MIN scheme depend not only on the configuration of MIN but also on another mechanism in the first proposed method. It results in low success probability for any request. The second proposed method releases this disadvantage. The following are the features of our two proposed schemes: (1) The full-access interconnection property; (2) Simple and distributed self-routing ability; (3) The least hardware cost; (4) Low reconstruction overhead.

We analyse the performance of a multistage interconnection network (MIN) with a packet-switching protocol, embedded in a closed network of processors. First, the expected value of transmission time through a delta-2 type of MIN is determined. We then obtain, for the first time by an analytical method, a formula for its probability density function from which the variance and higher moments follow. Previously densities have only been estimated by simulation which is expensive and can be unreliable, especially in the often crucial tail region. Numerical results reveal new insights into the hot-spot phenomenon which occurs when one output address is selected more frequently than the others. We first show how mean transmission time on hot paths increases with the hot-spot intensity and compare this with cooler paths. We also plot the density functions for these transmission times. Hence it is possible to determine precisely transmission time variability and to obtain reliability measures from their tails. The approach can handle arbitrary routing frequencies to the MIN output addresses and suggests new approximation techniques with wider applicability.

Patel (1981) proposed a probabilistic approach to analyze the performance of synchronous multistage interconnection networks (MINs) based on a uniform reference model and the assumption of independent requests. Patel's model and analytical results have been widely adopted by numerous researchers as a basis to investigate various aspects of MINs. We study in detail the effects of the independence assumption on the accuracy of system performance and point out the factors which cause an inaccuracy. A new queueing model is then proposed and is shown to be very accurate. Since only six states are needed, independent of the size of MINs, this new model is very efficient computationally.

VA-DE: Valuable ATAPE with dynamic embedding and super-pipeline scheduling on partitionable multistage interconnection [formula omitted

A generalized architecture is presented for reconfigurable m-ary tree structures, where m is any integer >1. The approach is based on a generalized multistage interconnection network (MIN), which is a generalization of the augmented shuffle-exchange MIN introduce by the authors previously (1990) for obtaining reconfigurable binary tree structures. The generalized architecture with m/sup k/ processing elements or nodes (where k is any integer >1) is implemented with a k-stage MIN. A single control code issued to the MIN establishes a distinct m-ary tree configuration among the nodes. The favorable features of the architecture include fast reconfiguration, simplified hardware in the nodes and the MIN, and simple routing control. The reconfigurability of the architecture is proved, and the results of the analysis are utilized to provide a procedure to synthesize the m-ary tree configuration that is generated for any given control code. Considerations for implementing the switching elements of the MIN are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>