Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design

With the aid of few directives and canonical forms, high-level synthesis (HLS) tools allow FPGA developers to describe their hardware designs in higher-level languages such as C or C++, thus enabling software engineers to exploit the powerful capabilities of FPGA-based accelerators. Hardware engineers may also benefit from automated RTL generation through HLS, as it can boost their productivity with shorter development cycles and simpler validation processes. However, the introduction of automation with its associated performance losses brings the viability of the current HLS-based approach into question: are we sacrificing the main advantage of FPGA designs, namely their performance, in return for higher productivity? This paper examines the performance-per-power penalties incurred in HLS designs in the context of stencil computations for fluid flow simulations, a prevalent class of applications that are difficult to accelerate because of their low arithmetic intensity. By using Xilinx’s Vivado HLS tool to replicate a hand-crafted RTL implementation of a solution of Laplace’s equation, this paper evaluates the impact of implicitly expressing parallelism, particularly if specific optimizations are not directly supported by the tool. In addition, by describing scenarios in which the HLS approach does and does not excel for stencil-based computations, this paper offers insights to assist hardware engineers in setting their expectations of the HLS approach and suggests alternative techniques to accomplish common tasks that fail or underperform using typical approaches.

Principal Component Analysis (PCA) is a widely used approach for dimensionality reduction in image processing. In microwave imaging, for example, it is used as an intermediate step toward image reconstruction. An FPGA hardware implementation of PCA is highly beneficial, especially as an accelerator for a low-cost embedded environment. In this paper we propose a flexible PCA hardware accelerator that can be used for different input data dimensions and input precisions. In addition, it supports both floating-point and fixed-point arithmetic representations. The target hardware is a ZYNQ SoC. We used High Level Synthesis (HLS) to quickly explore the design space and so to find the best implementation for a given setting of the application parameters and given the characteristics of the target hardware. We show the impact on performance of different hardware optimization techniques enabled by HLS. The proposed method outperforms a similar state-of-the-art HLS design in terms of latency and resource usage.

We ask the question, “should High-level Synthesis (HLS) design be part of an undergraduate computer engineering education while learning digital system design?”. Current trends in industry include an increasing demand for engineers who can build FPGA systems. FPGAs, just like other chips, continue to improve in terms of complexity, speed, available resources, and new features. The design complexity for using an FPGA continues to grow and Hardware Description Languages (HDLs), though a step up in design efficiency compared to schematic design, is a low-level approach akin to assembly language for programmers, and HDLs limits the productivity of an engineer. HLS tools, such as Legup, Intel HLS, and Xilinx's Vivado attempt to provide designers with a higher-level design abstraction providing a means to describe their computation in high-level languages - such as C. As these tools become more mainstream in industry, when should education follow? In this work, we explore how HLS tools might be used by an undergraduate by looking at exemplar designs, a simple RISC-V processor and a basic C loop, and implementing the design in both HDL and HLS. We then analyze the FPGA cost of each implementation. Next, we provide a philosophical discussion based on this experience on what the pros and cons of moving students to HLS design abstraction level are.

High-level synthesis (HLS) allows hardware designers to think algorithmically and not have to worry about low-level, cycle-by-cycle details. This provides the ability to quickly explore the architectural design space and tradeoff between resource utilization and performance. Unfortunately, evaluating the security is not a standard part of the HLS design flow. In this work, we aim to understand the effects of HLS optimizations with respect to power side-channel leakage. We use Vivado HLS to develop different cryptographic cores, implement them on a Xilinx Spartan 6 FPGA, and collect power traces. We evaluate the designs with respect to resource utilization, performance, and side-channel leakage through power consumption. Furthermore, we analyze the first-order leakage of the HLS-based designs alongside well-known register transfer level (RTL) cryptographic cores. We describe an evaluation procedure for hardware designers and use it to make insightful recommendations on how to design the best architecture in cryptographic domain.

Today's linear algebra and machine learning applications (ML) continue to grow in size and complexity, placing rapidly increasing demands on the underlying hardware and software systems. To address these issues, hardware designers have proposed using custom accelerators explicitly designed for these demanding workloads. However, realizing the full potential of custom accelerators requires effective hardware/software (HW/SW) co-design strategies that enable seamless integration and optimization across both domains, which is currently a major challenge in accelerator development. This thesis presents an integrated solution to facilitate HW/SW accelerator design. We also address issues in accelerator deployment, enabling rapid prototyping, integrated benchmarking, and comprehensive performance analysis of custom accelerators. In this thesis, we demonstrate the value of a lightweight system modeling library integrated into the build/execution environment of a production ML runtime engine, leveraging TensorFlow Lite for deployment. We explore custom accelerators performance by analyzing the trade-offs between various design choices, including parameter settings and accelerator configurations, from small to large scale, to identify the most effective combinations for specific workloads. Secondly, we employ the Multi-Level Intermediate Representation (MLIR) compiler framework to automatically partition host code from accelerator code, pre-optimizing the latter for improved high-level synthesis (HLS) designs and high-quality accelerated kernels. Lastly, we present compiler extensions to automate the generation and optimization of communication between the host CPU and AXI-based accelerators. We present novel solutions that enable more efficient and effective design space exploration, optimization, and deployment of custom accelerators. The utility of these approaches is demonstrated through experiments with specific accelerator designs and key linear algebra and ML workloads. Most importantly, these solutions empower high-level language users, such as domain scientists, to participate in the design of new accelerator features.--Author's abstract

In digital signal processing, digital down converters (DDCs) convert digitized, band-limited signals to lower frequency signals at a smaller sampling rate to simplify subsequent filtering stages. Software-defined radio (SDR) is a radio communication system in which components that are traditionally implemented in hardware are implemented in software on an embedded system. DDCs are widely used in modern communication systems, such as SDRs. Herein, we propose a low-power- and area-optimized implementation of a DDC for SDR applications. The DDC was designed using an innovative and novel high-level synthesis (HLS) design method based on application-specific bit widths for data nodes. The results achieved after a field programmable gate array (FPGA) implementation are superior to those obtained from hand-coded register transfer level (RTL) implementations in terms of area and power efficiency, with almost the same speed of operation. Our results were obtained using the MATLAB hardware description language (HDL) coder for HLS and Xilinx Vivado (a software for the synthesis and analysis of HDL designs) for synthesis. The DDC down-converts an input of 200 MHz signal to an output of 2 MHz signal. This implementation was conducted on a real FPGA hardware (Xilinx Kintex-7) and verified against the design specifications using an FPGA in the loop feature of HDL Verifier and MATLAB. In addition, we propose a generic methodology for improving the area, speed, and power for different application designs and HLS tools. The proposed methodology is also applicable to hand-coded RTL designs for any application.

This thesis introduces a novel approach to rapid Design Space Exploration (DSE) and presents a formalized High Level Synthesis (HLS) design flow with multi parametric optimization issues related to DSE such as the precision of evaluation, time exhausted during evaluation and also automation of the exploration process. During DSE a conflicting situation always exists for the designer to concurrently maximize the accuracy of the exploration process and minimize the time spent during DSE analysis. This technique is capable of drastically reducing the number of architectural variants to be analyzed for accurate selection of the optimal design point in a short time. The DSE results for many benchmarks are presented along with a comparison to an existing DSE approach that uses the hierarchical structure method for architecture evaluation. Results indicated significant improvement in speedup compared to the current existing approach.

In recent years, domain-specific accelerators (DSAs) have gained popularity for applications such as deep learning and autonomous driving. To facilitate DSA designs, programmers use high-level synthesis (HLS) to compile a high-level description written in C/C++ into a design with low-level hardware description languages that eventually synthesize DSAs on circuits. However, creating a high-quality HLS design still demands significant domain knowledge, particularly in microarchitecture decisions expressed as pragmas. Thus, it is desirable to automate such decisions with the help of machine learning for predicting the quality of HLS designs, requiring a deeper understanding of the program that consists of original code and pragmas. Naturally, these programs can be considered as sequence data. In addition, these programs can be compiled and converted into a control data flow graph (CDFG). But existing works either fail to leverage both modalities or combine the two in shallow or coarse ways. We propose ProgSG, a model that allows interaction between the source code sequence modality and the graph modality in a deep and fine-grained way. To alleviate the scarcity of labeled designs, a pre-training method is proposed based on a suite of compiler's data flow analysis tasks. Experimental results show that ProgSG reduces the RMSE of design performance predictions by up to 22%, and identifies designs with an average of 1.10× and 1.26× (up to 8.17× and 13.31×) performance improvement in design space exploration (DSE) task compared to HARP and AutoDSE, respectively.

Field-Programmable Gate Array (FPGA) based hardware accelerators offer reconfigurability, performance, adaptability, and good energy efficiency. The majority of Convolutional Neural Network (CNN) based inference systems are initially developed using standardized frameworks like PyTorch, Tensor Flow, and more. These Python or Python-like models can be mapped on FPGAs to build accelerators. Mapping frameworks to port designs on an FPGA convert the CNN models to high-level languages like C/C++ or OpenCL so that standard tools like high-level synthesis can facilitate the mapping of models on an FPGA. The logic utilization and performance of FPGA-based accelerators are dependent on the CNN network parameters, architectural selection (data-flow, pipelined, etc.), and synthesis-based control of design generation. A scalable multi-layer CNN hardware accelerator is modeled in Vitis 2020 HLS tool. Early estimation of performance and hardware resources helps choose the best CNN network before those are executed for time-consuming high-level synthesis and physical design mapping for FPGAs. We present various Machine Learning (ML) models to estimate the Logic Utilization and Computation Time from the Python design descriptions of CNNs. Our results show a very successful and accurate estimation for performance and resource utilization over various multi-layer CNN networks in negligible time before running HLS synthesis.

Technology scaling into subnanometer range will create process variations which have impact on the overall manufacturing yield and quality. At the same time System-on-Chip (SoC) complexity and communication requirements are increasing which will make a SoC designer goal to design a fault-free system a very difficult task. The dependability will be an important measure of System-on-Chip design process. As a result we see a shift from bus based systems into networked systems and from traditional Register Transfer Level (RTL) design paradigm into higher abstraction levels — High Level Synthesis (HLS) and system-level design. In real-time networked systems the dependability cannot be reached effectively without predictable contention free communication synthesis. In this paper, an approach that takes into account flow control unit(s) transmission latencies over actual links, is extended to cover, in addition to virtual cut-through, also wormhole switching and wormhole switching with virtual channels. The communication synthesis results are used in our proposed system-level design methodology for dependable realtime Systems-on-Chip.

A large semantic gap between the high-level synthesis (HLS) design and the low-level (on-board or RTL) simulation environment often creates a barrier for those who are not FPGA experts. Moreover, such low-level simulation takes a long time to complete. Software-based HLS simulators can help bridge this gap and accelerate the simulation process; however, we found that the current FPGA HLS commercial software simulators sometimes produce incorrect results. In order to solve this correctness issue while maintaining the high speed of a software-based simulator, this paper proposes a new HLS simulation flow named FLASH. The main idea behind the proposed flow is to extract the scheduling information from the HLS tool and automatically construct an equivalent cycle-accurate simulation model while preserving C semantics. Experimental results show that FLASH runs three orders of magnitude faster than the RTL simulation.

As clock speed increases taper off and hardware designers struggle to scale parallelism within a chip, software developers and researchers must face the challenge of writing portable software with no clear architectural target. On the hardware side, energy considerations will dominate many of the design decisions, and will ultimately limit what systems and applications can be built. This is especially true at the high end, where the next major milestone of exascale computing will be unattainable without major improvements in efficiency.Although hardware designers have long worried about the efficiency of their designs, especially for battery-operated devices, software developers in general have not. To illustrate this point, I will describe some of the top ways to waste time and therefore energy waiting for communication, synchronization, or interactions with users or other systems. Data movement, rather than computation, is the big consumer of energy, yet software often moves data up and down the memory hierarchy or across a network multiple times. At the same time, hardware designers need to take into account the constraints of the computational problems that will run on their systems, as a design that is poorly matched to the computational requirements will end up being inefficient. Drawing on my own experience in scientific computing, I will give examples of how to make the combination of hardware, algorithms and software more efficient, but also describe some of the challenges that are inherent in the application problems we want to solve. The community needs to take an integrated approach to the problem, and consider how much business or science can be done per Joule, rather than optimizing a particular component of the system in isolation. This will require rethinking the algorithms, programming models, and hardware in concert, and therefore an unprecedented level of collaboration and cooperation between hardware and software designers.

Background: In recent years, the rising demand for high-performance radar systems in aeronautics, astronautics, national defense, and civil communication has driven the widespread application of phased-array technology. The design of beam controllers, the core of phased-array systems, faces many challenges. Traditional implementation schemes are usually based on application-specific integrated circuits (ASIC) or discrete components, which have a long development cycle, poor flexibility, and limited adaptability. Field-programmable gate arrays (FPGA), with their high parallelism, reconfigurability, and powerful signal processing capabilities, offer a new way to implement phased-array control systems. But FPGA design has traditionally relied on register transfer level (RTL) description, which is inefficient and struggles to keep up with the rapid iteration of complex algorithms. With the development of high-level synthesis (HLS) technology, it has become possible to develop FPGAs using high-level languages such as C/C++. However, improving development efficiency while ensuring hardware performance remains a key issue in the design of phased-array beam controllers. Materials and Methods: This study employs an HLS - RTL co - design method to build a phased - array beam controller. This approach combines the strengths of HLS's efficient algorithm implementation and RTL's precise hardware interface control. The system architecture consists of three parts: the host - machine control layer, FPGA processing layer, and phase - control output layer. In the FPGA processing layer, the core beam - forming algorithm is implemented via HLS. Based on phased - array principles, this algorithm converts target angles to wave vectors and calculates phase - compensation values for each element in an 8×8 array. Pipelining and parallel processing techniques are used in the HLS design to optimize algorithm throughput and latency. The phase - control output layer, designed with RTL, repackages 64 calculated phase values and distributes them to 16 physical phase - shifter chips. Each phase - shifter manages four elements and receives control data through an SPI interface. Results: The proposed FPGA-based phased-array beam controller design in this paper has successfully achieved high - speed, high - precision beam control. By using the HLS - RTL co - design method, it has solved the problem of low algorithm implementation efficiency in traditional FPGA development and ensured the high performance and reliability of hardware interfaces. Experimental results indicate that the system meets or surpasses design targets on key performance indicators. Its end - to - end latency is kept within 130μs, it supports an angle update rate of over 5,000 times per second, and can satisfy the requirements for tracking highly dynamic targets in practical applications. Conclusion: The major contributions of this research are as follows: presenting an HLS - RTL co - design methodology for complex FPGA system development; designing an efficient phased - array beam - forming algorithm and its hardware implementation; and developing a flexible and scalable phased - array control system architecture that supports different array configurations. These findings are highly significant for beamforming technologies in phased - array radar and 5G communication systems, as well as for other FPGA applications requiring high - speed signal processing.

High-level synthesis is a powerful tool for increasing productivity in digital hardware design. However, as digital systems become larger and more complex, designers have to consider an increased number of optimizations and directives offered by high-level synthesis tools to control the hardware generation process, resulting in a large design space to be explored. One of the most impactful optimizations is loop pipelining due to its large improvement in the hardware throughput. Nevertheless, the modulo scheduling algorithms that are used for loop pipelining are computationally expensive, and their application to the whole design space can make its exploration inviable, leading to sub-optimum solutions. Current state-of-the-art tools for modulo scheduling follow an iterative approach, which solves O(n^2) optimization problems, where n is the loop code size. To address this problem, this work proposes a novel data-flow-based approach that solves exactly 2 optimization problems, independently of the loop code size. Results show orders-of-magnitude savings in the computation time, leading to significant design space exploration time savings when compared with the state-of-the-art. As such, the proposed method produces hardware designs of higher performance than the ones produced by the current state of the art for large and complex loops, maintaining a similar resource utilization.

Due to the rapidly increasing complexity in hardware designs and competitive time to market trends in the industry, there is an inherent need to move designs to a higher level of abstraction. Behavioral Synthesis is the process of automatically compiling such Electronic System Level (ESL) designs written in high-level languages such as C, C++ or SystemC into Register-Transfer Level (RTL) implementation in hardware description languages such as Verilog or VHDL. However, the adoption of this flow is dependent on designers' faith in the correctness of behavioral synthesis tools. Loop pipelining is a critical transformation employed in behavioral synthesis process, and ubiquitous in commercial and academic behavioral synthesis tools. It improves the throughput and reduces the latency of the synthesized hardware. It is complex and error-prone, and a small bug can result in faulty hardware with expensive ramifications. Therefore, it is critical to certify the loop pipelining transformation so that designers can trust the behaviorally synthesized pipelined designs. Certifying a loop pipelining transformation is however, a major research challenge because there is a huge semantic gap between the input sequential design and the output pipelined implementation, making it infeasible to verify their equivalence with automated sequential equivalence checking (SEC) techniques. Complex loop pipelining transformations can be certified by a combination of theorem proving and SEC: (1) creating a certified pipelining algorithm which generates a reference pipeline model by exploiting pipeline generation information from the synthesis flow (e.g. the iteration interval of a generated pipeline) and (2) conduct SEC between the synthesized pipeline and this reference model. However, a key and arguably, the most complex component of this approach is the development of a formal, mechanically verifiable loop pipelining algorithm. We show how to systematically construct such an algorithm, and carry out its verification using the ACL2 theorem prover. We propose a framework of certified pipelining primitives which are essential for designing pipelining algorithms. Using our framework, we build a certified loop pipelining algorithm. We also propose a key invariant in certifying this algorithm, which links sequential loops with their pipelined counterparts. This is unlike other invariants that have been used in proofs of microprocessor pipelines so far. This dissertation provides a framework for creating certified pipelining algorithms utilizing a mechanical theorem prover. Using this framework, we have developed a certified loop pipelining algorithm. This certified algorithm is essential in the overall approach to certify behaviorally synthesized pipelined designs. We demonstrate the