Monolithic integration of photonic and electronic circuits in a CMOS process

Joseph F. AhadianClifton G. Fonstad, Jr.Massachusetts Institute of TechnologyDepartment of Electrical Engineeringand Computer Science77 Massachusetts AvenueRoom 13-3030Cambridge, Massachusetts 02139E-mail: joeah@oevlsi.mit.eduAbstract. Optoelectronic very large scale integrated (OE-VLSI) circuitsare a basic component of optical interconnects proposed to overcomethe limitations of high-speed electrical interconnects. Epitaxy-on-electronics (EoE), a monolithic integration technology capable of com-bining thousands of optoelectronic devices with VLSI-complexity GaAsElectronics, is reviewed. The fundamental assumptions on which theEoE technology is founded are explained and the development of theEoE integration process is reviewed. Then, the recently completedOPTOCHIP research foundry project, which made LED-based optoelec-tronic integrated circuits (OEICs) available to optical interconnect re-searchers, is described. Finally, integrated LED, photodetector, and cir-cuit characterization results are detailed. These results show the utility ofEoE OEICs in implementing optical interconnect architectures and pointout current performance limitations.

The development of semiconductor optoelectronics devices will have great impact on optical computing. Progress in semiconductor lasers and photodetectors has revolutionized communication systems and realized new methods of memory, printing and other processes. Further advances in optoelectronic devices, which are now taking a new integrated form, optoelectronics integrated circuit (OEIC). The OEIC will make possible highly versatile optical computing systems in the next century. Recent developments in OEIC technology and future prospects for its application to optical computing are presented.

Novel monolithic optical receivers in 0.8-mm standard MOS technology with non-return-to-zero data rates in excess of 531 Mbit/s at 850 nm are introduced. At 638 nm the data rates are above 622 Mbit/s. The innovative integrated double and pin photodiodes allowing this high speed without any modification in a CMOS process are described, and results for their quantum efficiency and for their transient response are presented. Furthermore, the improvement of the sensitivity of the photo- diodes and of the optoelectronic integrated circuits (OEICs) by an anti- reflection coating is discussed. The circuit topology of several OEICs is described. A transimpedance input stage with an active MOS feedback resistor is implemented. Analytical calculations for the bandwidth and for the overall transimpedance of several amplifiers as well as measured results are presented. Finally, an OEIC in a 1.0-mm CMOS technology with a polysilicon resistor instead of a MOS feedback resistor with a data rate of 1 Gbit/s for 638 nm is shown. The sensitivity of this OEIC is improved by at least 9 dBm over that of published OEICs. © 2003 Society

The design, fabrication, and performance of the highest speed optoelectronic integrated circuit (OEIC) receivers reported to date are presented. These consist of PIN detectors and AlGaAs/GaAs HBT transistors fabricated on the same GaAs substrate. The p-i-n detectors were made from the same base and collector epitaxial layers as used for the HBT transistors and were completely compatible with the authors' usual transistor fabrication process; no process alteration was required. The authors report 20-mm detectors with 35.6% quantum efficiency, 40-nA dark current at -3-V bias, and bandwidth in excess of 17 GHz. These detectors were used to produce two OEIC receivers, one with a bandwidth of 6.7 GHz and an equivalent input noise current of 4.3 pA/Hz/sup 1/2/ and another with a bandwidth of 13 GHz and an equivalent input noise current of 10 pA/Hz/sup 1/2/. The performances of a variety of circuit topologies are compared, and the effect of different epitaxial layer structures on OEIC performance is investigated. >

Optoelectronic integrated circuits (OEICs) in which both optoelectronic and electronic devices are monolithically integrated can exhibit various advantages in improving performance, functionality and reliability. This review concerns the development of OEICs based on GaAs systems. The requirements of integration include the development of devices having high performance and structures suitable for integration, and fabrication techniques for planar, process-compatible integrated structures. Superior devices such as low-threshold-current quantum-well (QW) lasers, planar-structure metal-semiconductor-metal (MSM) photodiodes and the planar integration process have been developed, and these have been used to fabricate multichannel transmit- and receive-OEICs operating at gigabit rates. The applications of such OEICs have been demonstrated in high-speed optical links and 4×4 optical switches. The technological areas expected to be developed further are discussed in view of the future widespread applications of OEICs to communication and signal-processing systems.

Silicon monolithically Optoelectronic Integrated Circuit (OEIC) designed in standard CMOS process has been gradually applied. But Spice models of opticalelectronic devices such as photodetector can not be provided by IC manufactories in OEIC design. A novel Spice model of photodetector is introduced for compatible-design of OEIC in this paper. An N⁺/N-Well/P-Sub photodetector in standard CMOS process is described. The model of CMOS photodetector is completely based on Hspice EDA design software. It includes optical current, dark current, junction capacitor, series resistor, parallel resistor, and even noise characteristic. A four-terminal network structure is utilized to take the place of the photodetector in the model. The whole model can be easily applied to OEIC design as a subcircuit. At 780nm wavelength, the characteristics of the N⁺/N-Well/P-Sub photodiode fabricated in 0.5μm CMOS process are simulated with the Spice model and tested. With a reverse bias of 2.5V, the measured and simulated responsivity is both about 0.25A/W, which indicates the availability of the model. Finally, the compatible-design of OEIC used for optical pickup unit in optical storage system has been accomplished with the novel photodetector model.

We realized different types of optoelectronic integrated circuits by integrating on the same silicon chip: photo detectors, linear or logic electronic circuits, waveguides, coupling elements. This paper present the design, modeling and experimental realization of these components, underlining the original approaches and results. Special structures of photo detectors were designed, in order to allow optical coupling with waveguides and monolithic integration with electronic and photonic circuits. Original models for these photo detectors were developed. The electronic circuits we realized, unlike those reported in literature, can operate at very low input currents. Also new materials and processes were studied and experimented in order to improve the component performance. Specific technologies for optoelectronic circuits, compatible with either CMOS or bipolar processes, were established by analyzing the relationships between the technological parameters and circuit characteristics. Also the matching with waveguides and micro mechanical structures technologies was analyzed and experimented, as the aim of our research activity was to realize different types of micro-electro- mechanical systems for sensor applications.

Optoelectronic monolithic integration is preferable for multigigabit transmission systems because of small waveform degradation due to interconnect parasitics in optoelectronic hybrid integration. Implementation of a wavelength division multiplexing subsystem on the optoelectronic integrated chip will further increase the transmission capacity in optical fibers. A five-wavelength integrated distributed feedback laser array with 50 A lasing wavelength separation has been developed. Multiquantum-wells are promising as a basic structure in future optoelectronic integration. They show high potential in low threshold current laser diodes, high-frequency modulators, and high-speed detectors.

Summary form only given. The first realization of the integration of HEMTs (high electron mobility transistors) and HBTs (heterojunction bipolar transistors) on an InP substrate is reported. Furthermore, the application of this technology to a receiver OEIC (optoelectronic integrated circuit) is demonstrated by integrating these devices monolithically with a p-i-n photodiode to form an OEIC comprising these three diverse components. This complex integration was made possible using the selective regrowth capabilities of OMCVD (organometallic chemical vapor deposition). The schematic cross section of a receiver OEIC thus obtained is shown. >

On-chip millimeter wave Wilkinson power divider has been developed with the back end of line (BEOL) wiring and enabled as a library device in a 0.13 mum BiCMOS process design kit. The device layout and model are fully scalable, i.e. users can design a power divider at different frequencies or in different reference characteristic impedance systems by inputting the dimensions. Excellent model and hardware correlation has been observed up to 110 GHz. The measured results show that very good performance on-chip Wilkinson power dividers have been obtained in this technology, such as less than about 0.1 dB amplitude imbalance, about 0.8 dB of insertion loss with bandwidth of about 15% of the design frequency (defined at 15 dB return loss level) and about 20 dB of isolations. In addition, the device is the design rule check (DRC) clean and the layout versus schematic (LVS) enabled, which help to shorten the design cycle.

G. Allen VawterSandia National LaboratoriesAlbuquerque, NM 87185-5800AB STRACTThe influence of processing on the design of optical devices and optoelectronic integrated circuits isdiscussed. Process compatibility of devices used as the basis of a complete optoelectronic integratedcircuit will be discussed along with some potential optoelectronic integrated circuits employing onlyphase modulators and couplers. Specific examples of the application of reactive-ion-beam etching in theformation of passive optical waveguide phase modulators, optical interconnects, turning mirrors, andoutput couplers in GaAs/AlGaAs are given.

Next-decade computing power and interconnect bottle-neck challenge conventional IC design due to the ever increasing demands for high frequency and great bandwidth. Three-dimensional large-scale integration (3D-LSI) provides an opportunity to realize such high performance cores while reducing long latency. In this paper, we present a reference flow for the implementation of 3D via-last ICs in scalable face-to-back bonding style which leverages a mature set of 2D IC physical design tools. The first enabling technology of 3D-LSI is through-silicon via (TSV). Two kinds of TSV diameters are exemplified in the flow, namely, 5µm and 50µm. We propose an easy-to-adopt method to address the TSV-aware mixed-sized placement by considering the obstructions generated from adjacent-tier's floorplan, subject to certain TSV alignment constraints. Furthermore, the technique of clock tree synthesis (CTS) for a homogeneous die stack is developed to dramatically reduce the clock latency and skew. The mixed-sized placement and CTS of each tier can be done without iteration. To the best of our knowledge, no work has ever been published in literature discussing CTS for 3D via-last integration in a face-to-back fashion. Finally, to complete the proposed flow 2D timing-driven routing and modified off-line design rule check (DRC) and layout versus schematic (LVS) verification are performed very well.

Recently, low-cost silicon optoelectronic integrated circuits (OEICs) have been drawing attention for applications in short-distance optical communications such as chip-to-chip and board-to-board interconnects, LAN, data storage networks, etc [1–4]. Particularly, single-chip OEICs with on-chip silicon photodiodes provide a number of advantages including low cost, reduced ground-bounce, and bond-wire-induced coupling. Nevertheless, the slow response of silicon photodiodes in a standard CMOS process serves as a major bottleneck for high-speed communication [1]. To improve the bandwidth of silicon photodiodes, either some process modification or avalanche photodiode implementation has been developed. However, the former results in increased costs, whereas the latter has reliability issues. Although a differential photodiode configuration was originally proposed for bandwidth extension [2–4], the operation speed is still limited to several-hundred Mb/s. Meanwhile, the bandwidth can be extended by exploiting equalization filter [1, 3]. For relatively low-Gb/s operations, fixed equalization filter is sufficient, because photodiode responsivity is dominantly determined by diffusion currents which are not sensitive to process and temperature variations. For higher speeds, the responsivity becomes strongly dependent on the process and temperature variations, because it is mainly determined by the carrier mobility. Thereby, equalizers for high-Gb/s optical receivers require an adaptation algorithm to compensate the significant process and temperature variations. In this paper, an OEIC with on-chip photodiode is presented. Bandwidth and responsivity are compensated by a compact adaptive equalizer, thus achieving 8.5Gb/s operation.

Epitaxy-on-electronics (EoE) optoelectronic integration technology is an economical GaAs VLSI process and monolithically integrates heterostructure devices such as emitters, detectors, or modulators to produce complex and manufacturable optoelectronic integrated circuits (OEICs). We explores EoE's short-term potential to produce 1 tera-bit/s/cm/sup 2/ smart pixel arrays. The issues of pixel density, processing complexity, electronic and optoelectronic bandwidth, and thermal management will be addressed in detail, along with the technical and economic advantages of using GaAs VLSI electronics rather than CMOS.

Organic light-emitting diodes (OLEDs) permit the monolithic integration of microelectronic circuits and light-emitting devices on the same silicon chip. By the use of integrated photodetectors, low-cost CMOS processes and simple packaging; economically produced optoelectronic integrated circuits (OEICs) with combined sensors and actuating elements can be realized. The OLEDs are deposited directly on the top metal layer. The metal layer serves as electrode and defines the bright area. Furthermore, the area below the electrodes can be used for integrated circuits. Due to efficient emitter with low operating voltage it is possible to renounce high-voltage devices depending on selected CMOS process. Thus manufacturing cost can be further reduced. Different CMOS metallizations were examined and their effects on organic light-emitting diodes were analyzed. Red (628nm) and orange (597nm) emitting p-i-n OLEDs with a radiance of 5W/m 2 sr at 2.8V and 3.0V and a half angle of ±45° were realized on metal layer with low roughness. Near infra-red emitters are in development. We will present an optical microsystem. The functionality of combined sensors and actuating elements as well as advantages and difficulties of the monolithic integration of OLEDs and CMOS will be discussed. The chip was manufactured in a commercial 1μm CMOS technology. The fabricated microsystem combines three different types of sensors: a reflective sensor, a colour sensor and a particle flow sensor.