MTSCStack: An effective technique to decrease leakage power in VLSI circuits

In the IoT for multi-sensor node application [1], there are demanded both high-performance for computation in an active mode, and an ultra-low standby power in a sleep mode for longtime buttery life in the energy efficient system. Ultra-low standby MCU with embedded NVM using 90 nm CMOS technology is also reported [2], but its SRAM cache is not sufficient for applying imaging processing which requires large memory capacity with imaging sensors in edge computing. Embedded SRAMs can be achieved fast read/write access within a few nanoseconds, but consume standby leakage power for data retention, being dominant power in the sleep mode. To reduce the standby leakage power of embedded SRAMs, the source bias design technique with power-gating is introduced on a bulk CMOS device [3]. In the resume standby (RS) mode, the VSS source bias control for SRAM array is demonstrated as an effective SRAM leakage power reduction. Besides, once the large SRAM array are into the resume standby mode, it takes long time to wake-up again. It is not applicable for high-speed CPU operation. Then, a fast resume standby mode (FRS) for cache memories is proposed to wake-up as much as fast. In that FRS mode, the power supply for SRAM peripheral is cutoff but SRAM array is keeping with a VDD supply. Each standby mode and its circuit diagram are summarized in Fig. 1. Meanwhile, dopant-less channel fully-depleted (FD) silicon-on-insulator (SOI) device is proposed [4]–[6] to improve the performance, power, and area (PPA) of embedded SRAMs. FD-SOI enables to control the back-bias (BB) dynamically under the buried-oxide (BOX) to reduce leakage current and/or to improve performance by applying reverse or forward bias, respectively. Fig. 2 presents the block diagram of BB control scheme for voltage scaling in IoT application with FD-SOI structure [7]–[9]. BBs for NMOS (VBN) and PMOS (VBP) can be applied individually by VBB generator (VBB Gen.) circuit. Four operation modes for smart IoT applications are considered. High-performance, normal, low-power operating modes are introduced, along with the required loads in the system. The sleep mode with SRAM data retention for long-term waiting in the sensor nodes is also proposed. Each supply voltage and BB is also shown in Fig. 2. The comparison of embedded SRAM leakage power is shown in Fig. 3.

Recent trends in CMOS technology and scaling of devices clearly indicate that leakage power in digital circuits would be crucial and largely depend on the sub-threshold currents. Minimizing leakage, by power gating logic circuits using sleep transistors gives considerable power savings. However, this technique cannot be used in sequential circuits and memory cells, as it would result in loss of stored data. In this paper, we propose a novel circuit by applying a self-bias transistor (SBT) to minimize sub-threshold leakage currents in static and dynamic circuits. This circuit with SBTs, acts as a smart switch by virtually power gating either pull-up or pull-down logic, and causes a considerable reduction in leakage currents in both active and standby modes. A benchmark is simulated with 0.18 /spl mu/m CMOS technology in the Cadence Spectre circuit simulator. Results show significant reduction in leakage power, of up to 50% on average, for all possible states simulated in static and dynamic circuits by applying this proposed self-bias transistor.

This paper presents SRAM circuit techniques to reduce both active and standby mode power especially at room temperature (RT) where actual power consumption is dominant. A bit line power calculator is used to adaptively set the cell supply voltage (VCS) in the active mode. A digitally controllable retention circuit regulates VCS in the standby mode with small control power. These circuits are implemented in a dual-power-supply SRAM in 28 nm CMOS technology. Compared with the conventional scheme, the power consumption in the active and standby mode at 25°C is reduced by 27% and 85%, respectively.

Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high-threshold voltage. A general leakage current model which has been verified by HSPICE simulations is used to estimate leakage power. Results show that the dual-threshold technique is good for leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, the leakage power can be reduced by more than 80%. The total active power saving can be around 50% and 20% at low- and high-switching activities, respectively.

Due to the continuous downsizing of metal oxide semi-conductor field effect transistor devices, power dissipation is one of the vital issues for the integrated circuit design. As a result of voltage scaling at lower technology nodes, threshold voltage decreases which results in increase in leakage current, hence leads to increase in leakage power dissipation. In this paper, a novel low leakage technique called LCINDEP (leakage control input DEPendent) is proposed for nano-scaled circuits. The device characteristics and hence overall performance gets affected due to increased power dissipation. Proposed LCINDEP technique is extensively demonstrated for low power operation and reliability analysis. Various short gate (SG) fin type field effect transistor (FinFET) logic circuits are simulated using LCINDEP technique and comparative analysis is performed with the already available leakage reduction techniques. The proposed LCINDEP technique provides reduced leakage power by 89.71% and 91.92% in LCINDEP SG FinFET NAND and NOR gates respectively with respect to the conventional SG FinFET NAND and NOR gates. Besides this benchmark circuits like ring oscillator and ISCAS-85 C17 show decrease in power dissipation by 24.75% and 35.5% respectively with LCINDEP technique in respect to the conventional FinFET circuits. Reliability analysis in terms of process voltage and temperature variations is performed using Monte Carlo Approach for 5000 samples, which also depicts that proposed LCINDEP technique is more reliable than the available low power techniques. The normalized standard deviations (σ/µ)% is improved by 54.68% and 43.93% for power delay product metric in the proposed technique compared to the conventional one for SG FinFET NAND and NOR gates respectively. All the simulations are performed at 16 nm technology node for FinFET logic devices using predictive technology model multigate based on BSIM-CMG on HSPICE tool.

Leakage current consumes the majority of the active mode energy in the high-performance integrated circuits of today. In particular, in high microprocessor and system-on-chip architectures, the SRAM cell array is the primary source of leakage current. So low-leakage SRAM design is essential. Today’s VLSI designs are all about cutting down on power dissipation, supply voltage, leakage currents, and chip area. However, raising these parameters increases sub-threshold leakage currents and power dissipation, reducing design performance. Increasing the cell area reduces leakage power dissipation in standby mode. To solve these problems, it is best to cut down on effective leakage currents and dynamic power dissipation. For low voltage and energy constraints, the power dissipation, area, and delay performance of the low-power design of the 6T-SRAM cell with the DTMOS technique for a proposed low-power SRAM will be implemented in the Tanner EDA tool in 22 nm technology. The power of both types of SRAM cells will be compared using low-power techniques and a power analysis.

Shrinking size of transistors has enabled us to integrate more and more logic elements into FPGA chips leading to higher computing power. However, it also brings serious concern to the leakage power dissipation of the FPGA devices. One of the major reasons for leakage power dissipation in FPGA is the utilization of prefetching technique to minimize the reconfiguration overhead (delay) in Partially Reconfigurable (PR) FPGAs. This technique creates delays between the reconfiguration and execution parts of a task, which may lead up to 44% leakage power of FPGA since the SRAM-cells containing reconfiguration information cannot be powered down. In this work, a resource management approach containing scheduling, placement and post-placement stages has been proposed to address the aforementioned issue. In scheduling stage, a leakage-aware cost function is derived to cope with the leakage power. The placement stage uses a cost function that allows designers to decide a trade-off between performance and leakage-saving. The post-placement stage employs a heuristic approach and shows further improvements. Experiments show that our approach can achieve large leakage savings for both synthetic and real life applications with acceptable extended deadline. Furthermore, different variants of the proposed approach can reduce leakage power by 40-65% when compared to a performance-driven approach and by 15-43% when compared to state-of-the-art works.

In this paper we propose a new approach Overdriving Input Voltage CMOS (OIV-CMOS) to suppress static power. We found that in comparison to the base inverter, leakage power dissipation is appreciably reduced by 99.66% in OIV-CMOS at 180nm CMOS technology. It is also observed that for 2:1 MUX, the standby mode power consumption is reduced by 65.8% without effecting the performance and area of the circuit.

In this paper, we present a methodology for systematically optimizing the power-supply voltage for either maximizing the performance of very large scale integration (VLSI) circuits or minimizing the power dissipation in technologies where leakage power is not an insignificant fraction of the total power dissipation. For this purpose, we develop simplified empirical equations that describe the transistor behavior as a function of power supply and temperature. We use these models to calculate the full-chip power dissipation as a function of power supply and temperature. We then solve the power and chip thermal equations simultaneously to calculate the chip temperature and power dissipation at a given power supply. By varying the power-supply voltage, we determine the optimum V/sub DD/ value that minimized delay per unit length in global interconnects and therefore maximizes performance. Using the same framework, by again varying the supply we find the optimum V/sub DD/ that minimized the total power dissipation while maintaining a given delay per unit length. We show that for 90- and 65-nm technologies, where leakage power represents a significant fraction of the total power dissipation, optimum V/sub DD/ for maximum performance is lower than the International Technology Roadmap for Semiconductors (ITRS) specified supply voltage. This is due to the fact that reducing V/sub DD/ results in a large reduction in total power dissipation, and therefore the chip temperature, which improves performance. This improvement in performance is greater than the performance penalty incurred due to reduction in V/sub DD/. We also show that as the required delay per unit length is increased, total chip power consumption is reduced significantly if the power supply is also reduced as compared to the case when power supply is fixed at the nominal value. This change becomes larger with technology scaling due to the fact that leakage power, which is a very strong function of chip temperature, becomes a larger fraction of the full-chip power dissipation.

In deep sub-100nm technologies, the exponential increase of static leakage current pose serious design challenges as we try to build efficient low power systems with faster memory cores. Consequently, it is imperative to design systems that adopt leakage control techniques during both standby and active mode. In the recent past, the size of memory cores also has been increasing at a very rapid pace to cope with the demands of high computing processors. Such large memory cores will lead to significant leakage power dissipation, as most of the devices will be in a dormant or standby mode. This study addresses the static current dissipation problem in an SRAM memory core, by implementing a combinatorial approach to reduce leakage current. In this approach we have combined multiple-Vth devices, high-oxide thickness devices and dynamic Vth techniques to reduce both subthreshold and gate-oxide leakage current. There is a ~60% savings in the total static current dissipated as compared to a conventional SRAM cell

If current technology scaling trends hold, leakage power dissipation soon becomes the dominant source of power consumption. Caches, due to the fact that they account for the largest fraction of on-chip transistors in most modern processors, are a primary candidate for attacking the leakage problem. While there has been a flurry of research in this area over the last several years, a major question remains unanswered. What is the total potential of existing architectural and circuit techniques to address this important design concern? In this paper, we explore the limits in which existing circuit and architecture technologies may address this growing problem. We find that by using perfect knowledge of the address trace to carefully apply sleep and drowsy modes, the total leakage power from the instruction cache may be reduced to mere 3.6% of the unoptimized case, and the total from the data cache reduced to only 0.9%. We also present a complete parameterized model to determine the optimal leakage savings while the implementation technology changes over time. We further suggest how such limits might be approached using a form of prefetching for low power.

Modern embedded systems are often severely resource-constrained. In current research, the reduction of dynamic power has been the focus. However, with increased chip speed and density in submicron scale, the static (leakage) power consumption has become an increasingly significant fraction of the total. Indeed, a five-fold increase in leakage power per technology generation has been observed. At this pace, leakage power could soon equal dynamic power. In this paper, we investigate scheduling policies to reduce leakage power in real-time systems. We show that with simple scheduling techniques, overall leakage energy can be reduced by an order of magnitude.

As per the International Technology Roadmap for Semiconductors (ITRS) the leakage power is growing exponentially and is the major part of total power consumption in the integrated device. With the growing impact of subthreshold and gate leakage, static leakage contributes more and more towards the power dissipation in deep submicron nano CMOS technology. To overcome this problem several techniques has been proposed. In this paper we analyses the subthreshold leakage minimization techniques in circuit level. We propose a circuit technique named “Feedback Sleeper-Stack (FS-S)” for efficient leakage reduction in digital circuits. The proposed technique is compared with available leakage reduction techniques for subthreshold power, total power, delay and PDP (Power Delay Product). Of the available techniques, three power gating techniques are considered for comparison namely, Sleeper, Forced Stacking (FS) and Sleepy Stack (SS). Nominal supply voltage of 0.9V is selected and 32nm BSIM4 Predictive Technology Models (PTM) is employed in the analysis. ELDO Mentor Graphics tool is used for net list simulation.

Arithmetic and Logic Unit (ALU) is a combination circuit that performs a number of arithmetic and logical operations within a microprocessor.We present guidelines for low- and ultra low-power & high performance 32- bit ALU [1] units and analyze structures for logical operations to determine the most suitable for these regions of operations for low power applications.An ALU design is then modeled in VHDL for further testing with pre-manufactured parts of the 32 bit ALU using XILINX ISE tools. A novel method that chooses better designs of flipflops and latches in different places of the data path, based on the data and clock activities.Our simulation results indicate that, for the 180nm-65nm CMOS technologies [6] it is possible to reduce the ALU total energy by 18%-24%, with minimal delay degradation. In addition, there is up to 22%-32% reduction in leakage power in the standby mode.

The stability, leakage power and speed of Static random access memory (SRAM) have become an important issue with CMOS technology scaling. In this paper, a controller circuit is introduced which is separately controlling the load, driver and access transistors of SRAM cell. Based on word line signal value, optimal body bias voltage is generated through control circuitry to control stability, leakage and speed in SRAM cell. The proposed cell gives faster read and writes with an improvement of 68.5% and 89.2% over conventional 6T SRAM cell. In standby mode, about 62.2% leakage power reduction is observed in [Formula: see text] array architecture of SRAM. The proposed cell is implemented with 65[Formula: see text]nm CMOS technology and exhibits higher hold and write margins with an improvement of 26.29% in hold margin and 16.6% improvement in write margin as compared to conventional 6T SRAM cell. Robustness of the proposed SRAM cell with respect to stability, leakage and speed are confirmed under process, voltage and temperature variations.