Multi-level attacks: An emerging security concern for cryptographic hardware

Hardware Trojans pose a significant threat to the security and integrity of cryptographic systems, particularly in Advanced Encryption Standard (AES) implementations, which are widely used in securing sensitive data. These malicious modifications to integrated circuits (ICs) can compromise the confidentiality and reliability of AES cryptographic operations by introducing covert backdoors, information leakage channels, or functional disruptions. Hardware Trojans are typically designed to evade detection during design-time validation and post-manufacturing testing, often activating only under specific triggers such as rare input patterns or environmental conditions. In AES systems, Trojans can manipulate the encryption process by leaking secret keys through side-channel information such as power consumption, timing variations, or electromagnetic emissions. Some Trojans directly alter the encryption algorithm, weakening the cryptographic strength and rendering encrypted data vulnerable to attacks. Attackers may also embed Trojans at the Register Transfer Level (RTL) or gate-level design, leveraging the inherent complexity of AES circuits to conceal their presence. Detection and mitigation of hardware Trojans in AES implementations are challenging due to their stealthy nature. Techniques such as side-channel analysis, functional verification, and static code analysis have been developed, but sophisticated Trojans often bypass these methods. Advanced countermeasures include runtime monitoring, hardware obfuscation, and Trojan-resilient design methodologies. This paper explores the implications of hardware Trojans in AES cryptographic systems, analysing their design, potential attack vectors, and impacts on data security. Furthermore, it discusses state-of-the-art detection and prevention techniques, highlighting gaps and future research directions. Given the critical role of AES in securing financial, military, and consumer data, addressing the hardware Trojan threat is paramount to ensuring trust in cryptographic hardware and safeguarding against adversarial exploitation.

The Consultative Committee for Space Data Systems (CCSDS) recommends AES algorithm as a cryptographic algorithm to maintain confidentiality and data security between spacecraft and ground systems. In implementation, there are several AES algorithm operating modes including Cipher-Block Chaining (CBC), Electronic Codebook (EBC), Cipher Feedback (CFB), Output Feedback (OFB), and counter mode (CTR). One of the operating modes of AES algorithm recommended by CCSDS is CTR because it has advantages in terms of efficiency of implementation and offers a high level of data security. LAPAN-A4 as the next generation of LAPAN satellites also uses CCSDS standard in terms of data exchange between satellites and ground stations including telemetry and telecommand (TTC) data and satellite payload data. In order to protect LAPAN-A4 satellite data, especially TTC data, in this paper AES algorithm was implemented in CTR operating mode on the FPGA which will then be implemented on LAPAN-A4 satellite onboard data handling (OBDH) as one of LAPAN-A4 satellite data security systems. To overcome the limited resource of FPGA, optimization is also done using basic iterative AES hardware reused method, which is to reuse hardware that has been designed n times for same operation for AES algorithm. From the results of implementation and optimization, efficiency of logic gates used is increasing almost a quarter less than the previous research.

This study discusses the effectiveness of using AES (Advanced Encryption Standard) and RC4 (Rivest Chipper 4) as digital data security algorithms to prevent and protect transaction data from irresponsible parties. This needs to be done because the development of sales transactions or other services has used digital technology a lot. This situation causes the need to secure digital data from existing transactions, so that transaction data can be stored safely. Transaction data security is carried out by changing data into ciphers or codes that are difficult to read using the AES (Advanced Encryption Standard) and RC4 (Rivest Cipher 4) algorithms. This research begins by collecting existing transaction data and then transforming it into ASCII code. The results of the transformation will be used to perform calculations using the AES algorithm. After completing the calculation process using the AES algorithm, then do the calculations using RC4. These results will be stored in the database so that the transaction data that has turned into these codes cannot be known by other parties. The combination of the AES and RC4 algorithms is carried out to strengthen data encryption because there are more and more rotation systems and double security is carried out so that digital data is not easily read and misused. With the presence of this research, it can be shown that the AES and RC4 algorithms are capable of encrypting existing transaction data with multiple levels of security.

Nowadays, an integrated circuit can carry many functions which make them more challenging to design and manufacture. The involvement of the third party is not unusual which can open the possibilities for unauthorized modification by inserting illegal block called hardware trojan to perform some malicious functions. This issue raises attention in the field of hardware security to prevent the insertion of the hardware trojan and to detect its presence in a chip. Side channel analysis is considered as a prospective method, although there are several difficulties encountered. In this paper, we will implement cryptographic hardware that can encrypt information using Advanced Encryption Standards (AES) in a Field Programmable Gate Arrays (FPGA). Then, this reference model is subjected to the implantation of hardware trojan designed to leak the AES key. By using the side channel analysis and by adjusting the behavior of the hardware trojan, we will try to detect its presence using conventional instruments available in our labs. In the end, we can conclude the possibility for the end customer to detect the existence of hardware trojan and the design techniques of hardware trojan to evade the detection.

ABSTRACTThe tremendous advancement in very large scale integration technology encourages chip designers to rely on commercial electronic design automation tools, offshore fabrication services, and outsourced intellectual property cores. As third-party involvement are more in chip design cycle, integrated circuits (IC) such as programmable logic devices (PLD) and application specific ICs (ASIC) are highly vulnerable to hardware Trojan (HT) attacks. HTs are malicious additions or modifications to existing circuit elements, which can be inserted at any stages of IC life cycle to modify/destroy the functionality, reduce reliability, leak sensitive information, etc. Besides, HT can be designed either as always on or triggered only under certain operating conditions. For example, HT attacks in safety critical applications such as nuclear power plant, space and defence will jeopardise the safety and security of the unit and cause serious consequences. Hence, it is most important to ensure that the chip being in use performs only the intended function. In this paper, an in-depth analysis of feasible HT attacks in PLD and ASIC life cycles are presented. Based on the extensive literature survey on HTs and their countermeasure techniques, the state of the art HT prevention, detection, and diagnosis techniques are recommended to the valid stages of PLD and ASIC life cycles. Therefore, incorporating possible HT defence solutions in respective phases of PLD/ASIC-based safety systems thwart them against HT attacks.

Side channel analysis(SCA) focuses on attacking cryptographic algorithm implementations by collecting leaked information and analyzing the correlation between the leaked and key information in the cryptographic system. Currently, SCA is the main threat to cryptographic implementations, with DPA (differential power analysis) and DFA (differential fault analysis) being two of the most threatening types of SCA. However, the existing countermeasures against DPA and DFA have shortcomings and can hardly protect cipher designs perfectly. Based on a comprehensive analysis of DPA and DFA, this paper proposes a new idea of using an evolutionary cipher (EVOC) against DPAs based on the model proposed by Kocher, and several different new types of DFAs. In fact, an EVOC is a kind of dynamic cipher designing method. Moreover, combined with intelligent searching algorithms and cryptography design policies, EVOCs utilize the dynamic and unpredictable properties of TRNG (a truly random number generator) to ensure cipher design at a high level of security. Therefore, with an EVOC we could design cryptography algorithms with high security to resist mathematical analysis as well as DPAs and DFAs. This paper analyzes and proves the security, efficiency, cost, and original features of EVOCs against DPA and DFA both theoretically and experimentally. Compared with existing countermeasures against SCAs, EVOCs use dynamic non-linear operations to destroy the bases of DPA and DFA. At the algorithm level, EVOCs are more efficient than other resistance methods. Based on the theory and experiments, this paper proposes certain modifications to the EVOC in the AES (advanced encryption standard) algorithm, which can be referenced by other dynamic designs of cryptographic algorithms.

Cryptographic devices with the Advanced Encryption Standard (AES) encryption algorithm are vulnerable to side channel attack, in particular, differential power analysis (DPA). Differential power analysis can be used to reveal the secret key in AES by monitoring the power consumption of the internal circuit and applying statistical processing. In this paper, an evaluation of power analysis attacks of six different AES Sbox designs, namely sum of product (SOP), product of sum (POS), table lookup (TBL), composite field (CF), positive polarity Reed-Miller (PPRM) and 3 stages PPRM, is presented. Comparison of the different AES Sbox implementations in terms of size, performance and SNR analysis is also performed. The results show that the composite field Sbox design is more resistant to attack and smaller than other Sbox designs but operates at a slower speed. This paper also presents a Random Clock mechanism that can be used to increase the resistance of the AES composite field Sbox design to power analysis attack by reducing the overall SNR by 78%.

Side-channel attacks, particularly differential power analysis (DPA) attacks, are efficient ways to extract secret keys of the attacked devices by leaked physical information. To resist DPA attacks, hiding and masking methods are commonly used, but it usually resulted in high area overhead and performance degradation. In this brief, a DPA countermeasure circuit based on digital controlled ring oscillators is presented to efficiently resist the first-order DPA attack. The implementation of the critical S-box of the advanced encryption standard (AES) algorithm shows that the area overhead of a single S-box is about 19% without any extra delay in the critical path. Moreover, the countermeasure circuit can be mounted onto different S-box implementations based on composite field or look-up table (LUT). Based on our approach, a DPA-resistant AES chip can be proposed to maintain the same throughput with less than 2K extra gates.

The meaning of security is to protect something important from not authorized peoples. Cryptography is one of the security systems. Many applications could be used in the security systems like military applications, email, banking, information technology of database. The proposed system uses advanced encryption standard(AES) with secure hash algorithms(SHA-1) to produce a strong ciphertext. Moreover, this paper make the combination of (SHA-1) which is a one way encryption, as a key with (AES) algorithm which is a two way encryption as a ciphering generator to obtain confidentiality and integrity, In this paper presented implementation of Advanced Encryption Standard (AES) and Secure Hash (SHA-1) Algorithm by the use of FPGA Hardware card, However implementation of the AES algorithm and SHA-1 using LABVIEW environment with MATLAB system generator to generate stream data to FPGA hardware target. The output of the hash function is used as an input key for AES in order to improve data security, From the algorithms result of AES and SHA-1 obtained in FPGA, the system obtained how it is simple in modeling hashing and AES algorithms, generating hash codes and plain texts in (small and capital letters), symbols and numbers. The FPGA card used in this system (Spartan 3AN)with frequency (50%), the complete system take (1,147)size from the available space of (11,776) and accuracy (90%),the system work properly.

Hardware Trojan detection techniques have been studied extensively. However, to develop reliable and effective defenses, it is important to figure out how hardware Trojans are implemented in practical scenarios. The authors attempt to make a review of the hardware Trojan design and implementations in the last decade and also provide an outlook. Unlike all previous surveys that discuss Trojans from the defender's perspective, for the first time, the authors study the Trojans from the attacker's perspective, focusing on the attacker's methods, capabilities, and challenges when the attacker designs and implements a hardware Trojan. First, the authors present adversarial models in terms of the adversary's methods, adversary's capabilities, and adversary's challenges in seven practical hardware Trojan implementation scenarios: in‐house design team attacks, third‐party intellectual property vendor attacks, computer‐aided design tools attacks, fabrication stage attacks, testing stage attacks, distribution stage attacks, and field‐programmable gate array Trojan attacks. Second, the authors analyse the hardware Trojan implementation methods under each adversarial model in terms of seven aspects/metrics: hardware Trojan attack scenarios, the attacker's motivation, feasibility, detectability (anti‐detection capability), protection and prevention suggestions for the designer, overhead analysis, and case studies of Trojan implementations. Finally, future directions on hardware Trojan attacks and defenses are also discussed.

Mobile ad hoc network (MANET) is a group of mobile nodes that communicates with each other without any supporting infrastructure. These networks have some unique features such as dynamic mobility, open nature, lack of infrastructure, limited physical security and they are vulnerable to several security threats. Malicious node can drop all or partial received packets instead of forwarding them to the next hop through the path. In order to find the malicious nodes, an initial transmission is made between the source and destination nodes. Using fuzzy rules, the trust value of each node is computed and it varies from 0 to 1. A common threshold value is set for each node and by using this threshold value, every node in the network can be identified as either a malicious node or a regular node. After identifying the malicious nodes, these nodes are eliminated by muting the power to off state. As the malicious nodes are eliminated between source and destination nodes, source node can select another trusted path to its destination
 node. For security and authentication of routing information, hybrid cryptography is employed, using advanced encryption standard (AES) and elliptic curve cryptography (ECC) algorithms. AES algorithm is used as symmetric algorithm to encrypt the routing information and ECC algorithm is used as asymmetric algorithm to encrypt the public key. During encryption, the original plain text is converted into cipher text with encrypted public key and similarly during decryption cipher text is converted into original plain text with decrypted private keys. So the proposed method involves both AES and ECC algorithms which provides security mechanism as efficient and sufficient one. The experimental simulations are carried for the proposed model using network simulator 2 (NS-2) for Throughput, Delay, Packet delivery ratio, Packet overhead and Packet drop.

An efficient AES implementation using FPGA with enhanced security features

In recent years, Hardware Trojans (HT)have become an increasing concern due to outsourcing the manufacturing of Implantable Medical Devices (IMDs). Power Analysis based Side-Channel Attack (SCA)is one of the main methods of detecting HT in IMDs. However, using SCA in detecting trojans is limited by the large process variation effects in IC technology which has reduced detection sensitivity of ultra-small trojans. Along with the safety of IMDs against HTs, the need for power management has also risen in parallel with the increasing complexity of IMDs. In this paper, we are analyzing the usefulness of Differential Power Analysis (DPA)resistant adiabatic logic gates to detect smaller trojans. DPA resistant adiabatic logic gates consume uniform power irrespective of input data transition and also consume lower power compared to conventional CMOS logic gates. When the HT is triggered in the DPA resistant circuits, the circuit will have non-uniform power consumption which will help us to easily identify HTs. In order to validate our proposed methodology, we have implemented a C17 and a carry save adder using a recently proposed DPA resistant adiabatic logic family called Energy-Efficient Secure Positive Feedback Adiabatic Logic Family (EE-SPFAL). Further, in order to calculate the true energy-efficiency of the EE-SPFAL logic, we have proposed a four phase Power Clock Generator (PCG)and integrated with the EE-SPFAL logic circuits. Simulations are performed in Cadence Spectre using 180nm CMOS technology. From our simulations, we have observed the non-uniform power consumption, during the activation of HT, in EE-SPFAL based C17 and carry save adder circuit. Further, EE-SPFAL based C17 and carry save adder along with its PCG consume 25.8% and 31.4% of less power as compared to the conventional CMOS based C17 and carry save adder respectively.

Hardware Trojans (HTs) are regarded as a security threat in the information society. HTs are unintentionally injected into LSI circuits by untrusted entities before the chip fabrication. HTs trigger malicious operations such as information leakage without designers noticing their operations. This paper proposes fine-grained power domain partitioning, which is a circuit design technique for detecting HT activities. This paper assumes a scenario where a fab injects HTs into the taped-out layout data and that circuit designers test the presence of HTs by using side-channel information (power consumption) of fabricated chips. Fine-grained power domain partitioning decomposes the power domain of target circuit into multiple power domains, enabling to effectively measure the small power consumption introduced by activities of tiny HTs. The measurement result using an HT-injected Advanced Encryption Standard (AES) circuit with fine-grained power domain partitioning shows that HTs can be detected.

The throughput of WPAN (Wireless Personal Area Network) based on Bluetooth was decided by the interference of Bluetooth piconets in the network. The interference was decided by the hamming correlation of Bluetooth FH (Frequency Hopping) selected sequence. In order to improve the WPAN throughput, the WPAN model and data packet collision model were built and the relations about WPAN throughput, the maximum hamming correlation of FH selected sequence, the numbers of Bluetooth piconets and the SNR of channel were analyzed. The functions of WPAN throughput were deduced. After analyzing the performance of Bluetooth FH selected sequence, the original algorithm was replaced by the AES (Advanced Encryption Standard) algorithm. The theoretical analysis proved that the AES FH sequences selected algorithm could improve the WPAN throughput. The simulation results proved the theoretical analysis. The test result with ARM926EJs SoC (System on Chip) + RF (Radio Frequency) chip nRF2401 and CSR's Bluecore4 Bluetooth module got the same conclusion. All of these could prove that the AES algorithm can improve the WPAN throughput efficiently.