Multi-Physics Coupling Analysis and Optimization Design of SiC MOSFET Power Module Package Insulation

This paper presents various issues related to a medium voltage power switch designed with series-connected transistors of the 1700 V/300 A SiC MOSFET power module. The focus of the paper are the voltage imbalance compensation methods: passive snubber circuits and active gate driving. Both methods are simulated in Saber software with the use of detailed models of the transistors and diodes of the module. At first, elements of the DRC snubber were determined and simulated during the double pulse procedure. Then, new active gate driver is proposed and verified via series of simulations. Finally, the test setup was designed with two series connected SiC MOSFETs inside CAS300M17BM2 power modules and experimental tests were performed at 1.5 kV DC to compare two compensation methods.

Emerging applications of compact high-voltage SiC modules pose strong challenges in the module package insulation design. Such SiC module insulations are subjected to both high-voltage dc and pulsewidth modulation (PWM) excitations between different terminals during different switching intervals. High <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dV/dt</i> strongly interferes with partial discharge (PD) testing as it is hard to distinguish PD pulses and PWM excitation-induced interferences. This article covers both the testing and modeling of PD phenomena in the high-voltage power modules. A high <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dV/dt</i> PD testing platform is proposed, which involves a super-high-frequency (SHF) (SHF >3 GHz) down-mixing PD detection receiver and a high-voltage scalable square wave generator. The proposed method captures SHF PD signatures and determines PD inception voltage (PDIV) for packaging insulation. Using this platform, this article provides a group of PDIV comparisons of packaging insulation under dc and PWM waveforms and discloses discrepancies in these PDIV results with respect to their excitations. Based on these PD testing results, the article further provides a model using the space-charge accumulation to explain the PD difference under dc and PWM waveforms. Both simulation and sample testing results are included in this article to support this hypothesis. With this new model, the article includes an updated insulation design procedure for the high-voltage power modules.

With the increasing application demands placed on high-voltage power modules, the insulation performance must be correspondingly enhanced. In particular, insulation failures and breakdowns initiated by partial discharge (PD) within the module are categorically intolerable. Therefore, making a comprehensive mechanistic understanding of module PD and the derivation of quantitative insulation-design guidelines indispensable. In this work, a chain-equivalent circuit model is established to rigorously analyze the electric-field–driven PD mechanisms in high-voltage power modules for the first time, fully elucidating the factors that distort the field at the triple point (TP). Under conditions dominated by the dielectric properties of the packaging materials, the partial-discharge inception voltage (PDIV) at TP scales proportionally with the square roots of ceramic thickness, package-material thickness, and their respective relative permittivity, while scaling inversely with the square root of the ceramic’s permittivity. The accuracy of the predicted correlations between structural-material parameters and PDIV are experimentally confirmed. Based on the chain- equivalent circuit model, an optimized structural– material parameter matching scheme is rapidly derived. Then a systematic insulation-design workflow is devised. The results of this study provide precise, quantitative guidance for the insulation design and material selection of high-voltage power-module substrates.

With the development of power modules for high voltage, high temperature, and high power density, their size is becoming smaller, and the packaging insulation experiences higher electrical, thermal, and mechanical stress. Packaging insulation needs to meet the requirement that internal electric field, temperature, and mechanical stress should be as low as possible. Focusing on the coupling principles and optimization design among electrical, thermal, and mechanical stresses in the power module packaging insulation, a multi-objective optimization design method based on Spice circuit, finite element field numerical calculation, and multi-objective gray wolf optimizer (MOGWO) is proposed. The packaging insulation optimal design of a 1.2 kV SiC MOSFET half-bridge power module is presented. First, the high field conductivity characteristics of the substrate ceramic and encapsulation silicone of the packaging insulation material were tested at different temperatures and external field strengths, which provided the key insulation parameters for the calculation of electric field distribution. Secondly, according to the mutual coupling principles among electric–thermal–mechanical stress, the influence of packaging structure parameters on the electric field, temperature, and mechanical stress distribution of packaging insulation was studied by finite element calculation and combined with Spice circuit analysis. Finally, the MOGWO algorithm was used to optimize the electric field, temperature, and mechanical stress in the packaging insulation. The optimal structural parameters of the power module were used to fabricate the corresponding SiC MOSFET module. The fabricated module is compared with a commercial module by the double-pulse experiment and partial discharge experiment to verify the feasibility of the proposed design method.

SiC MOSFET allows higher temperature capability with higher switching efficiency than that of conventional Si devices, due to its superior electrical and thermal properties. Nevertheless, there are few reports on the systematic characterization of the SiC MOSFET power module operating at high-temperature. In this paper, a SiC MOSFET power module with planar interconnection was designed and fabricated to achieve low parasitic inductance and improved thermal performance. The static and dynamic performance of the SiC power module were characterized at 200°C. The thermal resistance of the double-sided cooling power module is 28.5% lower than that of the one with single-sided cooling.

SiC MOSFET power modules are becoming global solution in environment harsh systems. Achieving reliability of such systems is of upmost importance due to large economic implications. Thereby, focus of this paper is ultimately improving the reliability of the SiC MOSFETS by bringing intelligence on the gate-driver (GD) with providing insight on real-time behaviour of relevant switch information. Device switch-current I d , apart from being used for short-circuit detection assessing the short-term reliability, in the combination with the on-state drain-to-source V ds,on enables possibility for the online junction temperature (T J ) estimation. The knowledge of T J can enable active thermal control and condition monitoring of the SiC MOSFET device such as state-of-health, remaining useful life, maintenance scheduling, etc. tackling the long-term reliability aspect. The T J model is obtained through calibration procedure, and stored in the FLASH memory located on the GD. With the aid of FPGA, developed look-up table is assessed, enabling real-time junction temperature monitoring for both devices in the commercial SiC MOSFET half-bridge module configuration.

Silicone gel is a prevailing material for encapsulation in insulated gate bipolar transistor (IGBT) power modules. The space charge transport behavior in silicone gel is significant to evaluate the electrical insulation characteristics. This paper focuses on the trap characteristics and electrical properties of the silicone gel, which were rarely studied before. The experiments are performed on the surface potential decay of silicone gel after the charge injection. Then, the energy distributions of electron or hole traps are determined by a double-trap energy level model, which can be fitted by the Gaussian distribution. In addition, the mobilities of positive and negative charges are determined, which are 1.38 × 10 −12 m 2 ·V −1· s −1 and 1.74 × 10 −12 m 2 ·V −1 ·s −1 , respectively. Furthermore, considering the heat as a byproduct resulting in thermal issues, the temperature-dependence of surface potential decay characteristics are also studied in this paper. When temperature rises, the decay rate of surface potential increases, especially when the temperature is higher than 80 °C. Finally, the contrastive analysis illustrates that the trap characteristics of silicone gel are between the trap characteristics in liquid-state material and solid-state material, which supports the phenomenon that silicone gel is more resistive to the sharp edges in power modules. This work can provide a useful reference for the design of encapsulation in high-voltage IGBT power modules.

This study discusses the approach of adaptatively regulating the surface charge and electric field distributions by nonlinear conductivity materials. Three groups of surface nonlinear conductivity (SNC) spacers, namely, SNC30, SNC60, and SNC90, were prepared by coating the epoxy (EP)/Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> spacers with EP/SiC composites of 30-, 60-, and 90-phr doping contents. Based on a downsized direct current gas-insulated transmission line (dc-GIL) model, the regulation effects of the SNC spacers are verified by changing the voltage waveforms and temperature gradients in both simulation and experimental studies. Results show impressive abilities of the SNC spacers on relaxing the electric field distortion by adaptively regulating the surface charge accumulation through nonlinear surface conduction. Under dc stress, the SNC spacers can significantly increase the discharge inception and the flashover voltages at room temperature. As the temperature gradient increases, the discharge suppression effects of the SNC spacers weaken first and then increase. Surface charges on the SNC60 and SNC90 spacers can make a rapid adjustment along with the polarity reversal voltage; the corresponding flashover voltages are improved by 18% and 29% compared with that of the original spacer.

Nano size semiconducting particles are the most commonly used fillers in field grading material to homogenize the inner electric field distribution. In this work, commercially purchased WS2 and the exfoliated ones were used as filler into EPDM to fabricate WS 2 /EPDM composites with different WS 2 loading. Nonlinear electric conductivities were measured at 25 50 and 80 respectively. The influence of temperature on the conductivity was introduced to analysis the conductivity changes of the WS2/EPDM composite at higher temperature. Direct current breakdown strength was also studied. Tests result shown that the properties of exfoliated WS 2 filled composite had more regular change and the best performance. It turned out that uniform size and morphology of filler will be helpful for the properties of composite. The nonlinear conductivity performance created the possibility of using WS2 as nonlinear conductivity filler in field grading material.

The robustness of SiC MOSFET body diode under extreme operating condition such as cryogenic and high temperatures becomes a crucial factor for high power/efficiency applications. In this paper, the dynamic performance of 1.2kV SiC MOSFET body diodes is systematically investigated from 90K to 603K. A double pulse test setup capable of controlling temperatures from 90K to 603K is used to measure device dynamic performance and extract parameters including recovery time ($\text{t}_{\mathbf {rr}}$), reverse recovery charge ($\text{Q}_{\mathbf {rr}}$), maximum reverse recovery current ($\text{I}_{\mathbf {rm}}$) and reverse recovery energy loss ($\text{E}_{\mathbf {rr}}$). The effects of gate resistance and load current on device dynamic performance are also examined.

Beside the nominal operating conditions defined for power semiconductors for different applications in form of currents to switch or voltage levels to block in many applications irregular operating modes might occur. Those might be triggered by known weaknesses of the surrounding system or more or less regularly, e.g. when a system starts up. Examples for this are brown outs in power supplies causing peak currents in PFC diodes, short circuits occurring e.g. during non-professional installation of systems, avalanche operation e.g. in case of unwanted high voltage or pulse stress to the body diode of SiC MOSFETs in traction applications. Partially, those known operating modes are covered by dedicated datasheet parameters. The paper will discuss the most prominent effect with respect to their impact on SiC devices.

High-temperature power electronics represent an increasing demand. Higher power density or severe ambient temperature applications become the trend, while silicon carbide components with 250-300 °C Tjmax are emerging. Among materials used in high-voltage power module, soft encapsulants play a significant role in improving both semiconductor die and module package voltage ratings, especially under enhanced electrical and thermal constraints. In operation close to their upper temperature limit, two silicone materials were selected among the most thermally stable soft insulators available today. Up to 300 °C, dielectric properties and their stability under isothermal aging in air ambient tests were characterized. The gel, tested using sandwich structures, exhibits cracking of its exposed-to-air face, at an aging temperature as low as 250 °C after less than 100 h. The elastomer, tested as free films, presents no cracking, no degraded electrical characteristics, and a 6 % relative mass loss, after 500 h aging. Moreover, the elastomer insulating properties, at low and high electric field, remains stable up to 300 °C (short-term tests), contrary to the gel which shows a strong increase in dc electrical conductivity. So the elastomer shows promising properties for improved encapsulation performance at 250 °C, to be further investigated in package configurations.

Characterization and monitoring of the faults in Wide Bandgap-based power modules are the prerequisites to achieve robust and reliable high density power electronic design. Due to the basic differences between wide bandgap and Silicon - based power modules, applying the existing condition monitoring approaches - which are mostly designed for Silicon-based devices - does not necessarily provide the expected accuracy in these circuits. Comprehensive and accurate reliability assessment can be addressed using condition monitoring techniques, specialized for wide bandgap-based devices. Real-time observation of the switch junction temperature, as the main failure indicator, is considered in this paper, and it has led to a more accurate estimation of the switch failure rate. In this paper, employing an iterative failure rate assessment with the capability to monitor the device condition and renew the assessment in specific time intervals has addressed the required condition monitoring criteria in wide bandgap-based devices. A coupled simulation platform, consisting of PLECS, COMSOL, and MATLAB is developed to obtain the switch operational parameters during an iterative realtime process. Bayerer lifetime model is employed to estimate the switch failure rate based on the real-time switch parameters. The developed real-time iterative condition monitoring technique is tested for a 1200V/50A SiC MOSFET power module as the case study. DSPACE is employed in the experimental setup as a high bandwidth signal interface, and it was shown that by employing the proposed condition monitoring technique, the switch failure rate can be acquired based on a real-time process in order to achieve more accurate reliability assessment during the switch operation.

This paper deals with static and dynamic measurements performed with full SiC MOSFET power modules. The voltage rating of the power modules is 1200 V and the current rating is 800 A. The on-resistances (R ON ) of the power modules were measured to be 6.0–10.0 mΩ, the measured blocking voltages were 1300–1400 V, and the threshold voltages were found to be around 3.0–3.5 V at 300 K. Evaluation of the dynamic performance has been carried out in a double-pulse tester with the use of commercially available gate drivers. A clean (i.e., almost oscillation and overshoot free) turn on and turn off transient behavior is obtained with negligible reverse recovery losses. The measured turn-on and turn-off losses at 800 V, 340 A, were 117 mJ and 40 mJ, respectively. With fixed supply voltage and load current, the energy-loss increases linearly with the gate resistance when varied from 2.5 to 20 mΩ. The energy losses remain insensitive with variation of temperature for a fixed supply voltage and current when tested up to the prescribed junction temperature of 150 oC.

The use of very high voltage power modules (> 10 kV) requires the implementation of appropriate structures for the device packaging. Particularly the triple point between the insulating substrate, the metallization and the encapsulation is subjected to strong electric field stress. A novel architecture is proposed for the metallized ceramic substrate. Its interest is validated by using finite element method simulations to analyze the electric field distribution inside the module. It is shown that creating a gap between the top electrodes thus forming mesa structures, enables a significant spreading of the equipotential lines. The resulting maximum electric field decreases exponentially versus the height of the mesa structure, with better results than when simply increasing the thickness of the ceramic in a conventional module structure.