Multiobjective search based algorithms for circuit partitioning problem for acceleration of logic simulation

A reconfigurable system is a system which may allow the service continuity under failure, on the basis of a reduced level of functionality. In such a system, when one component fails the rest of the system keeps working with some acceptable performance degradation. To distinguish between the normal behavior and the degraded one, the production rate is used as a performance measure. Two optimization problems dealing with reconfigurable systems are addressed. We consider a series system consisting of N stochastically independent components. Different technologies are assumed to be available for each component. The following design problems are studied: (i) Find the configuration which allows maximizing the production rate of the system under resource constraints. (ii) Find the configuration that allows to reach some predetermined level of production rate at minimal cost.

Over the last several years, uniprocessor systems, in an effort to overcome the limits of deeperpipelining, instruction-level parallelism and power dissipation, evolved from one processing coreto tens or hundreds of cores. At the same time, multi-chip systems and Systems on Board (SoB),have started giving their place to Systems on Chip (SoC) that exploit the latest nanometertechnologies. This has also caused a tremendous shift in the system development process towardsembedded systems, hardware/software co-design, SoC designs, multi-core designs, and hardwareaccelerators. Nowadays, one of the key issues for continued performance scaling is thedevelopment of advanced CAD tools that can efficiently support the design and verification ofthese new platforms and the requirements of today’s complex applications. This thesis focuses on three important aspects of the system development process: hardware/software partitioning, simulation and verification. Since the time consumed in those tasks is usually a large percentage of the overall development time, speeding them up can significantly reduce the ever important time to market. Hardware emulation on FPGAs has been widely used as a significantly faster and moreaccurate approach for the verification of complex designs than software simulation. In this approach, Hardware Simulation Accelerator and Emulator co-processor units are used to offloadcalculation-intensive tasks from software simulators. One of the biggest problems however is thatthe communication overhead between the software simulator, where the behavioral testbenchusually runs, and the hardware emulator where the Design Under Test (DUT) is emulated, isbecoming a new critical bottleneck. Another problem is that in a hardware emulation environmentit is impossible to bring outside of the chip a large number of internal signals for verificationpurposes. Therefore, on-chip observability has become a significant issue. Finally, one more crucial issue is the decision that has to be made on how to partition the system components into two distinct sets: those that will be implemented in hardware and those that will run in software. Inthis thesis we analyze all the aforementioned problems and propose novel techniques that can beused to attack them. First, we introduce a novel emulation framework that automatically transforms certain HDL parts of the testbench into synthesizable code in order to offload them from the software simulator and, more importantly, minimize the aforementioned communication overhead. In particular, we partition the testbench running on the software simulator into two sections: the testbench HDL code that communicates directly with the DUT and the rest, C-like, testbench code. The former section is transformed into synthesizable code while the latter runs in a general purpose CPU. Next, we extend this architecture by adding multiple fast scan-chain paths in the design in order to provide full circuit observability and controllability on the fly. Finally, we develop a fullyautomated hardware/software partitioning tool that incorporates a novel flow with new costmetrics and functions to provide fast and efficient solutions. The tool employs two separatepartitioning algorithms; Simulated Annealing (SA) and a novel greedy algorithm, the GroupingMapping Partitioning (GMP). Our experiments demonstrate that our methodologies provide cost-effective solutions for the hardware/software partitioning and emulation of large and complex systems.

A formal methodology for automatic hardware-software partitioning and co-scheduling between the muP and the FPGA has not yet been established. Current work in automatic task partitioning and scheduling for reconfigurable systems strictly addresses the FPGA hardware, and does not take advantage of the synergy between the microprocessor and the FPGA. In this work, we consider the problem of co-scheduling task graphs on reconfigurable systems. The target systems have an execution model which allows any subtask that can run on the FPGA to also run on the microprocessor, and allows reconfigurability of the FPGA (subject to area, performance, resource, and timing constraints). In this paper, we introduce a methodology for automatic co- scheduling using a proposed heuristic algorithm for hardware/software co-scheduling, ReCoS. It will be shown that the proposed algorithm provides up to an order of magnitude improvement in scheduling and execution times when compared with hardware/software co-schedulers found in related fields such as embedded systems, heterogeneous systems, and reconfigurable hardware systems.

PurposeIncreasingly complex and sophisticated VLSI design, coupled with shrinking design cycles, requires shorter verification time and efficient debug method. Logic simulation provides SoC verification with full controllability and observability, but it suffers from very slow simulation speed for complex design. Using hardware emulation such as FPGA can have higher simulation speed. However, it is very hard to debug due to its poor visibility. SOC HW/SW co‐verification technique seems to draw a balance, but Design Under Test (DUT) still resides in FPGA and remains hard for debugging. The purpose of this paper is to study a run‐time RTL debugging methodology for a FPGA‐based co‐verification system.Design/methodology/approachThe debugging tools are embedded in HDL simulator using Verilog VPI callback, so signals of testbench and internal nodes of DUT can be observed in a single waveform and updated as simulation runs, making debugging more efficient. The proposed debugging method connects internal nodes directly to a PCI‐extended bus, instead of inserting extra scan‐chain logic, so the overhead for area is reduced.FindingsThis method provides internal nodes probing on an event‐driven co‐verification platform and achieves full observability for DUT. The experiment shows that, compared with a similar method, the area overhead for debug logic is reduced by 30‐50 per cent and compile time is shortened by 40‐70 per cent.Originality/valueThe proposed debugging technique achieves 100 per cent observability and can be applied to both RTL and gate‐level verification. The debugging tool is embedded into HDL simulator using Verilog VPI callback, so DUT signals are displayed together with testbench signals in the same waveform viewer. New value of DUT signal is read from FPGA whenever it changes, which allows run‐time debug.

In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA device by counting the number of logic blocks, however this is not accurate with the increasing diverse resource types in the new FPGA architectures. We first propose a network flow based method to optimally check whether a circuit or a subcircuit is feasible for a set of available heterogeneous resources. Then the feasibility checking procedure is integrated in the FM‐based algorithm for circuit partitioning. Incremental flow technique is employed for efficient implementation. Experimental results on the MCNC benchmark circuits show that our partitioning algorithm not only yields good results, but also is efficient. Our algorithm for partitioning with complex resource constraints is applicable for both multiple FPGA designs (e.g., logic emulation systems) and partitioning‐based placement algorithms for a single large hierarchical FPGA (e.g., Actel′s ES6500 FPGA family).

Scalability planning for reconfigurable manufacturing systems

Comments on “A new heuristic approach for optimal reconfiguration in distribution systems” in 81 (2011) 282–289

In recent years, the verification of digital designs has become one of the most challenging, time consuming and critical tasks in the entire hardware development process. Within this area, the vast majority of the verification effort in industry relies on logic simulation tools. However, logic simulators deliver limited performance when faced with vastly complex modern systems, especially synthesized netlists. The consequences are poor design coverage, delayed product releases and bugs that escape into silicon. Thus, we developed a novel GPU-accelerated logic simulator, called GCS, optimized for large structural netlists. By leveraging the vast parallelism offered by GP-GPUs and a novel netlist balancing algorithm tuned for the target architecture, we can attain an order-of-magnitude performance improvement on average over commercial logic simulators, and simulate large industrial-size designs, such as the OpenSPARC processor core design.

This paper presents a new approach for the optimal reconfiguration of radial distribution systems in the presence of reactive power compensators (RPCs). The proposed method is based on the simultaneous reconfiguration and RPC allocation for the mitigation of losses, equalizing the feeder load balancing as well as improving the voltage profile in power distribution networks. In this paper, the compensators are the capacitor bank and distribution static compensator, which is a type of distribution flexible alternating current transmission system device representative of conventional and modern RPCs. In this regard, the optimal states of the distribution system tie switches are determined taking into consideration the best size and location of the RPCs. In order to facilitate the algorithm for multiobjective search ability, the optimization problem is formulated for minimizing fuzzy performance indices. Since the optimization problem is nonlinear, using intelligent search methods such as the shuffled frog-leaping (SFL) algorithm can overcome the limitations of conventional analytic methods. In addition, to enhance the performance of the standard SFL, the fuzzy frog-leaping rule is used in this paper. This algorithm is more accurate and has an efficient convergence property compared to other intelligent search algorithms. The proposed method is validated using the IEEE 33-bus test system and a Tai-Power 11.4-kV distribution system as a real distribution network. The obtained results indicate that multiobjective simultaneous placement of RPCs along with reconfiguration can be more beneficial than separate single-objective optimization.

General purpose parallel processing machines are increasingly being used to speed up a variety of VLSI CAD applications. This paper addresses logic simulation on parallel machines by exploiting the concurrency in the circuit being simulated (called data parallelism) as opposed to exploiting parallelism inherent in the simulation algorithm itself (called functional parallelism). The most crucial step in obtaining the maximum parallelism using data parallelism is the partitioning of circuit elements. We introduce a cost function which tries to model the simulation of a logic circuit in a parallel environment. The cost function tries to estimate the parallel run time for logic simulation given the processor assignment and the underlying multiprocessor architecture. We then present different heuristic algorithms to partition the circuit and evaluate the efficiency of these algorithms using the proposed cost function. Partitioning algorithms for both event-driven and compiled code simulation are given.

Multi-Objective Invasive Weed Optimization – An application to optimal network reconfiguration in radial distribution systems

본 논문에서는 재구성 가능한 시스템에서 Y-chart 설계공간 탐색 기법을 응용하여 하드웨어 소프트웨어 분할문제를 해결하기 위한 방법론을 제시하고 이 방법에 기초하여 성능분석 도구를 개발하였다. 이 방법론은 어플리케이션모델의 각 Task들로부터 범용프로세서나 FPGA와 같은 하드웨어 요소들로의 사상의 경우들을 생성하고 각각의 사상의 경우에 대한 시뮬레이션을 수행하여 시스템의 성능을 평가한다. 시뮬레이션 결과로 산출된 처리율에 기초하여 가장 좋은 성능을 산출하여 사상의 경우를 선택할 수 있다. 본문에서는 또한 시뮬레이션 속도를 향상시키기 위하여 작업량과 병렬성과의 관계에 기초하여 사상집합의 크기를 줄이는 휴리스틱 알고리즘을 제안한다. 제안된 사상집합 축소 휴리스틱을 적용한 시뮬레이션 결과 사상집합의 크기를 80%가량 줄일 수 있었다. In this paper, we propose a methodology solving the problem of the hardware-software partitioning in reconfigurable systems using a Y-chart design space exploration and implement a simulator according to the methodology. The methodology generates a mapping set between tasks and hardware elements using the hardware element model and the application model. We evaluate the throughput by simulating cases in each mapping set. With the throughput evaluation result, we can select the mapping case with the highest throughput. We also propose an heuristic improving the simulation time by reducing the mapping set on the basis of the relationship between workload and parallelism. Simulation results show that we can reduce the size of mapping set which poses difficulties on hardware-software partitioning by up to 80%.

In reconfigurable systems, reconfiguration latency is a very important factor which impact the system performance. In this paper, a framework is proposed that integrates the temporal partitioning and physical design phases to perform a static compilation process for reconfigurable computing systems. A temporal partitioning algorithm is proposed which attempts to decrease the time of reconfiguration on a partially reconfigurable hardware. This algorithm attempts to find similar single or pair of operations between subsequent partitions. Considering similar pairs instead of single nodes brings about less complexity for routing process. By using this technique, smaller reconfiguration bit-stream is obtained, which directly decreases the reconfiguration overhead time at the run-time. A complementary algorithm attempts to increase the similarity of subsequent partitions by searching for similar pairs and using a technique called dummy node insertion. An incremental physical design process based on similar configurations produced in the partitioning stage improves the metrics over iterations.

This study introduces a multi-criteria optimization approach using the Grey Wolf Optimizer (GWO) algorithm to determine the optimal capacity, locations of DG units and capacitor banks, and network reconfiguration in distribution systems. The objective function incorporates six key performance metrics: real losses, imaginary losses, voltage variation, voltage stability index, section load ability, and current balancing index. The proposed GWO technique was evaluated on IEEE 33- and 69-bus systems and benchmarked against Genetic Algorithm (GA) and Particle Swarm Optimization (PSO). Results demonstrate that GWO effectively optimizes the placement and sizing of DGs and capacitor banks under diverse conditions, enhancing system performance and reducing active power losses.

A multi-unit resource allocation system usually contains several processes and a number of resources with multiple units. Due to the competition for shared resources in these systems, deadlocks may occur. Recently, researchers have shown an increased awareness in deadlock control strategies for such a kind of systems without considering the dynamic changes such as processing failures and rework by using the Petri net paradigm. This article reports a new strategy for deadlock analysis and control in reconfigurable multi-unit resource systems (MRSs). We discuss a generalized class of Petri nets in which each stage of a process may require a number of units of different types of resources to perform a task. In this way, we can model more complex real systems. Thanks to a generalized class of Petri nets, i.e., the system of sequential systems with shared resources (S <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> R), this article proposes an effective integrated strategy for designing robust supervisors for reconfigurable MRSs, and improves an S <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> R model to achieve a new model, namely a system of sequential systems with shared resources and part-re-entry (S <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> RP), which represents the procedure that a flawed product re-enters a system and is re-processed. We use a siphon-based max-controllability deadlock prevention policy (DPP) to supervise the evolution of the S <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> RP, and present a comprehensive analysis to demonstrate that the controlled S <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> RP is free of deadlocks. A net analysis tool (INA) is used to test and validate the resulting S <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> RP.